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I've been doing a little research into this but I cannot find anywhere on how to divide a frequency 3 by 3 using JK flip flops, only this:

http://www.falstad.com/circuit/e-divideby3.html

But it is a D Flipflop.

I know how to divide by 2, 4, 8..etc

But how do I go about building a circuit to divide by 3?

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  • \$\begingroup\$ you can use a 3 bit ring counter but it won't give 50% duty cycle \$\endgroup\$ – nidhin Oct 31 '15 at 13:13
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    \$\begingroup\$ I think you will need to clock at least one FF on the positive edge, and one FF on the negative edge. \$\endgroup\$ – Wouter van Ooijen Oct 31 '15 at 13:20
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The only way to divide by an odd number and get a 50% duty cycle output is to use both edges of the clock signal, and this requires that the clock itself have a 50% duty cycle as well.

For example:

schematic

simulate this circuit – Schematic created using CircuitLab

There's no advantage to using J-K flip-flops for this; the circuit is exactly the same, with the J inputs connected where the D inputs are, and the K inputs tied high.

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    \$\begingroup\$ Your statement about how to connect a J-K flip-flop as a D flip-flop is not correct. For example, see circuitstoday.com/flip-flop-conversion#JKtoD . I'll delete this comment after you have corrected your answer. \$\endgroup\$ – Dwayne Reid Oct 31 '15 at 14:57
  • \$\begingroup\$ Thanks but I need to know how to do this with JK flipflops as I havn't learned about D Flipflops yet, Is it not possible to do this or something? everywhere I look on the internet it's done by D Flipflops \$\endgroup\$ – Modrisco Oct 31 '15 at 16:05
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    \$\begingroup\$ @DwayneReid: I never said, nor intended to imply, that the connection I described was a general way to replace a D flip-flop with a J-K flip-flop. I just described a connection that works for this circuit only. \$\endgroup\$ – Dave Tweed Oct 31 '15 at 16:57
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    \$\begingroup\$ @Modrisco: That's because nobody designs with J-K flip-flops any more. It's an obsolete technology of only academic interest at this point in time. All substantial new logic design is done with HDLs (hardware description languages), which are all D flip-flop based. \$\endgroup\$ – Dave Tweed Oct 31 '15 at 17:04
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    \$\begingroup\$ Which part of the last part of my answer do you not understand? \$\endgroup\$ – Dave Tweed Oct 31 '15 at 17:15

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