2
\$\begingroup\$

I wrote few lines of code and it is giving error. The code is below:

module tb();  
wire [7:0] m1,m2,m3;   
reg [7:0] a,b,c;   
reg en;     
reg clka=0;   
s_three call(m1,m2,m3,a,b,c,en,clka);   
always begin   
 #10 clka<=~clka;        
end      

initial begin    
en<=1'b1;    
a<=8'h00;   
b<=8'haf;   
c<=8'ha2;   
end     
endmodule           

module s_three(m1,m2,m3,a,b,c,en,clka);                                              
input [7:0] a,b,c;                       
input en,clka;                            
output [7:0] m1,m2,m3;               
wire [7:0] m11,m12;                          
s1 s0(m11,m12,a,b,en,clka);                      
endmodule         

The error given below:

ERROR:HDLCompiler:329 - "tb.v" Line 29. Concurrent assignment to a non-net a is not permitted

ERROR:Simulator:778 - Static elaboration of top level Verilog design unit(s) in library work failed

How can I resolve it ?
Thank you

\$\endgroup\$
  • \$\begingroup\$ Where is line 29 in the code you posted? \$\endgroup\$ – toolic Oct 31 '15 at 13:22
  • \$\begingroup\$ Sorry the mention line no 29 is s_three call(m1,m2,m3,a,b,c,en,clka); This the line in which it is pointing the error. \$\endgroup\$ – Shine_flower Oct 31 '15 at 13:24
  • \$\begingroup\$ And what is the module declaration for s_three? (i.e. what are the inputs and outputs) \$\endgroup\$ – Tom Carpenter Oct 31 '15 at 13:41
  • \$\begingroup\$ You show the definition for a module called s_three_1, but in your testbench, you instantiate a module called s_three -- giving it an instance name of call, which is confusing at best. \$\endgroup\$ – Dave Tweed Oct 31 '15 at 13:57
  • \$\begingroup\$ it was s_three ... I corrected Can you have idea how can i remove the error as i post ? \$\endgroup\$ – Shine_flower Oct 31 '15 at 14:06
4
\$\begingroup\$

Right, so what is happening is you have declared your module as this:

module s_three(m1,m2,m3,a,b,c,en,clka);                                              
input [7:0] a,b,c;                       
input en,clka;                            
output [7:0] m1,m2,m3;               
wire [7:0] m11,m12;

Now you might expect the ports to be connected in the order they appear in the brackets, but this is actually not so, they need to be connected in the order they are declared by the input ..., output ... lines, i.e. the implicit connection order for your module will actually be:

s_three call(a,b,c,en,clk,m1,m2,m3)

As a result you are connecting up your ports in a way you aren't expecting which can lead to funny errors. In this case outputs are connected to inputs, the register c is connected to an output (bad!), etc.


Implicit connection of ports is a debugging headache and while it saves a little bit of typing you really should avoid it for your own sanity when it comes to testing things. Also if you happened to want to add a new port, or change them around later on, anything that is implicitly connected would break.

To solve the problem, you should use explicit connections. For example the following explicitly connects the pins:

s_three call(.m1(m1),.m2(m2),.m3(m3),.a(a),.b(b),.c(c),.en(en),.clka(clk));   

The connections are described as: .portInModule(signalToConnect). By doing it this way it doesn't matter what order they appear. This would work just as well:

s_three call(.clka(clk),.en(en),.a(a),.b(b),.c(c),.m1(m1),.m2(m2),.m3(m3));   
\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.