I have created a VHDL module that continuously generates a one-bit wide pattern of "1010101010..." as long as it's enable bit input is asserted high, as part of a class assignment. In the description of the assignment, the justification given for creating this module is that they are used in many devices, and an example is the Ethernet I1 preamble, which consists of eight repeating octets of "10101010".
Here is my simulation result:
I understand the usefulness of the preamble for synchronizing packets, but I got the impression from my instructor's description that hardware designers will write modules like this to generate this pattern without referring to it as a "clock divider", even though it essentially is one. Why not just call it a clock divider instead of a "preamble_generator" or other such names?