0
\$\begingroup\$

How can I port out/in a register file with Verilog (synthesis-able code). At this specific code a generate loop code is not viable due to the architecture of an existing code.

A test code, trying to port to/from my module a dynamic register file, with size based on a parameter.

module mux_test (/*AUTOARG*/
   // Outputs
   ro,
   // Inputs
   clk, rst_n, ain, v, din, bias
   ) ;
   parameter D_WIDTH=8;
   parameter A_WIDTH=2;
   localparam N = 1 << A_WIDTH;

   input wire clk, rst_n;
   input wire [A_WIDTH-1:0] ain;
   input wire               v;
   input wire [D_WIDTH-1:0] din;
   input wire [D_WIDTH-1:0] bias[N-1:0];
   output reg [D_WIDTH-1:0] ro[N-1:0];

   wire [D_WIDTH-1:0]       d2s    = din + bias[ain];

   integer                  i;
   always @(posedge clk, negedge rst_n)
     if (!rst_n)
       for(i=0; i<N; i=i+1)
         ro[i] <= 0;
     else if (v)
       ro[ain] <= d2s;

endmodule // mux_test

The model-sim gives me the following:

-- Compiling module mux_test

** Error: ..../mux_test.v(3): (vlog-2110) Illegal reference to memory "ro".

** Error: .../mux_test.v(5): (vlog-2110) Illegal reference to net array "bias".

\$\endgroup\$
1
\$\begingroup\$

With Verilog you cannot have an input or output port with more than one dimension - so you can't declare a 2D array to be an input or output.

Instead you need to pack the array into a single dimension which can be done using a generate loop.

\$\endgroup\$
1
\$\begingroup\$

SystemVerilog will allow multi-dimensional ports and should be synthesizable.

module mux_test #(
parameter D_WIDTH=8,
parameter A_WIDTH=2 )
(  // Outputs
   output reg [D_WIDTH-1:0] ro[N-1:0],
   // Inputs
   input wire clk, rst_n,
   input wire [A_WIDTH-1:0] ain,
   input wire               v,
   input wire [D_WIDTH-1:0] din,
   input wire [D_WIDTH-1:0] bias[N-1:0]
   );

   localparam N = 1 << A_WIDTH;

   always @(posedge clk, negedge rst_n)
     if (!rst_n)
       for(int i=0; i<N; i=i+1)
         ro[i] <= 0;
     else if (v)
       ro[ain] <= d2s;

endmodule : mux_test
\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.