In my recent project, I need to design digital logic gates using TFET instead of CMOS logic. Can someone Suggest any simulator or procedure which support design using TFET logic?
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1\$\begingroup\$ You should probably read the TFET papers and/or ask in academic/research circles. Not many people here doing that. Probably this one in particular: dx.doi.org/10.1109/TCSII.2009.2035274 \$\endgroup\$ – Fizz Nov 2 '15 at 18:08
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\$\begingroup\$ I apologize as I seem to be late and you are probably already past this, but I gave a suggestion answer for future people. \$\endgroup\$ – mcmiln Feb 1 '16 at 17:46
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It would seem there is a simulator called NEMO5 I will also link in the paper which called this out... https://www.e3s-center.org/pubs/187/Huang_David.pdf
