Differential signalling 'traditionally' involves two conductors carrying equal and opposite signals, the data being signalled by the polarity. In this arrangement the majority of the current returns through one or the other conductor and the common-mode current is minimal (noise and whatever is coupled from the conductors). Current Mode Logic is also a differential signalling technique, but in this case each conductor either sinks or does not sink current. The current never changes direction and returns along the same path.
My question is, why should we try to impedance match a differential pair connecting CML devices? Does differential impedance even mean anything since the conductors will never carry equal and opposite signals?\$^1\$ Would it not be better to treat each conductor individually and match them to the single ended impedance of the devices?\$^2\$
(1) If we take EEWeb's definition that differential impedance "is measured between the two lines when they are driven with opposite polarity signals".
(2) While still taking into account cross-talk from elsewhere on the board, length matching, etc