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Differential signalling 'traditionally' involves two conductors carrying equal and opposite signals, the data being signalled by the polarity. In this arrangement the majority of the current returns through one or the other conductor and the common-mode current is minimal (noise and whatever is coupled from the conductors). Current Mode Logic is also a differential signalling technique, but in this case each conductor either sinks or does not sink current. The current never changes direction and returns along the same path.

My question is, why should we try to impedance match a differential pair connecting CML devices? Does differential impedance even mean anything since the conductors will never carry equal and opposite signals?\$^1\$ Would it not be better to treat each conductor individually and match them to the single ended impedance of the devices?\$^2\$

(1) If we take EEWeb's definition that differential impedance "is measured between the two lines when they are driven with opposite polarity signals".

(2) While still taking into account cross-talk from elsewhere on the board, length matching, etc

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My question is, why should we try to impedance match a differential pair connecting CML devices? Does differential impedance even mean anything since the conductors will never carry equal and opposite signals?

You have to dislocate the DC scenario from the superimposed AC signalling. Numerically the current may not reverse but, as far as sending data down a balanced pair of wires you need a balanced load.

Would it not be better to treat each conductor individually and match them to the single ended impedance of the devices?

However, twisted pair is a tad notorious because it tends to require a balanced load that is not only transverse but longitudanal as well so, your 2nd quote does carry a certain amount of decent weight of truth.

In my experience with +100Mbps data signalling I've tended to fall towards treating a piece of twisted pair as two individual wires and used 2 balanced load impedances connected to screen.

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  • \$\begingroup\$ Thanks Andy! Could you elaborate on what you mean by balanced though? I understand why differential impedance is important in traditional systems: the transmission line made up by the conductors is a single load and must match the impedance of the source to avoid reflections. With CML though, the load/transmission line is the single-ended trace and the return path (e.g. reference plane), right? I see why the propagation must be identical in each conductor, not why this impedance - from one conductor to another - must match the source? Where do reflections come from if its not? \$\endgroup\$
    – sebf
    Nov 2, 2015 at 19:01
  • \$\begingroup\$ The version of CML that I understood is differential: en.wikipedia.org/wiki/Current-mode_logic \$\endgroup\$
    – Andy aka
    Nov 2, 2015 at 20:20
  • \$\begingroup\$ That is the one I mean, but if you look at the schematic for a transmitter what I takeaway is, that while it is differential in the sense that the signals are complementary, they are not equal and opposite: de.wikipedia.org/wiki/Current_Mode_Logic#/media/… \$\endgroup\$
    – sebf
    Nov 2, 2015 at 20:38
  • \$\begingroup\$ The transient part of the signal is meant to be differential and both are opposite. \$\endgroup\$
    – Andy aka
    Nov 2, 2015 at 20:39
  • \$\begingroup\$ I was looking for a diagram to explain myself better and accidentally found one which cleared up my misunderstanding:en.wikipedia.org/wiki/FPD-Link#/media/… I had in my mind the DVI variant, which has termination resistors at the receiver only. This made it hard to see that the two pairs are indeed connected through the receiver buffer load, and that current is sunk from both pull-ups, not just the 'active' one. \$\endgroup\$
    – sebf
    Nov 2, 2015 at 21:20
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Whenever you use differential signals, it makes sense to analyze the circuit from a standpoint of 'common mode' and 'differential mode' signals. Let's say the 'low' current is 5 mA and the 'high' current is 10 mA. Yes, these are not opposite. However, if the signal is DC balanced (equal parts high and low on average, which is the case for most high speed serial links) then you can split this into the differential part and the common mode part. The common mode would be the average of the two - in this case, 7.5 mA. The differential part is the difference between the two - in this case, +/- 2.5 mA. So you get a common mode DC current of 7.5 mA with a differential current of either + or - 2.5 mA, depending on if the line is high or low. The differential mode is equal and opposite. The impedance of the transmission line only makes a difference for the changing part of the signal - in this case, the differential mode only. So yes, you most certainly do need to use proper impedance control techniques here.

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