# How to reduce SPI bit errors between a Bus Pirate and a BIOS chip?

I need to eliminate bit errors when reading a BIOS chip using a Bus Pirate v3.6.

The BIOS chip is still soldered onto the motherboard. I'm using a Bus Pirate probe set to connect the Bus Pirate to a SOIC test clip.

Here's a diagram:

laptop  ---usb--->  bus pirate  ---probes---> ---clip--->  BIOS IC


The motherboard has power but is not booted (the computer's power supply is plugged in but the computer is not turned on). I needed to plug in the computer to power the BIOS chip; powering the BIOS from the Bus Pirate didn't work (maybe because the Bus Pirate's weak power supply was trying to power the whole motherboard via the BIOS VCC pin).

Using flashrom I can read the BIOS chip, except I get lots of bit errors (about one every 400k bits). The Bus Pirate is configured to use a 30kHz clock (the lowest setting).

Is there anything I can do to reduce the bit error rate without desoldering the SOP8 BIOS chip?

Bus Pirate SPI settings:

• Clock polarity: "Idle low" (CPOL=0, I think). (The other option is "Idle high".)
• Output clock edge: "Active to idle". (The other option is "Idle to active".)
• Input sample phase: "Middle". (The other option is "End".) I'm not sure what this means, but "Middle" is the default.
• Output type: "Normal (H=3.3V, L=GND)". (The other option is "Open drain (H=Hi-Z, L=GND)".)

Unfortunately flashrom has the above settings hard-coded, so if they're not right for my BIOS chip then I'll have to edit the source code and recompile.

• Are you sure you are using the right SPI mode? – crasic Nov 3 '15 at 0:51
• @crasic: Updated my question. – Richard Hansen Nov 3 '15 at 0:58
• SPI mode is correct. The bios chips supports Mode 0 and Mode 3. You settings are Mode 0 (CPOL=0, CPHA=0). Note that "Active to Idle" means the edge where the clock goes from its active value to its idle value (the idle value being the clock polarity setting). – Tom Carpenter Nov 4 '15 at 17:29