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So I have this PMOS Common Source. I thought I'd make it a Voltage Follower by simply pulling it down to ground. But when SPICE-ing, whatever value the pull down resistor I give, it just won't work as a Voltage Follower.

Is it maybe because the V_in is ideal and assumed to provide the expected voltage no matter how much current is drawn out of it?

schematic

simulate this circuit – Schematic created using CircuitLab

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  • \$\begingroup\$ To make PMOS buffer(I assume you refer as Voltage follower) needed configuration is common Drain. You can not use common source as buffer/Voltagefollower. Or may be I did not quite understand your question. \$\endgroup\$ – Alper91 Nov 3 '15 at 8:47
  • \$\begingroup\$ No, you got it right. What I'm doing is probably just not industry standard (drawing too much current from input), where we usually want a very high input impedance. I just wanted to use PMOS as my calculations show it performs better than an NMOS Common Drain as a Buffer. \$\endgroup\$ – Derpy_Merp Nov 3 '15 at 9:58
  • \$\begingroup\$ You confused me again :) While NMOS buffer is Common Source, PMOS buffer is Common Drain. In your biasing, input impedance is like 10 ohm, not high impedance. Also, PMOS uses much more Gate area comparing to NMOS(Like 3 times of NMOS) so input impedance of PMOS is less than NMOS due to larger input Capacitance. Can you explain your statement in more detail? \$\endgroup\$ – Alper91 Nov 3 '15 at 10:28
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You generally make it a voltage follower by taking the output from the source - your output is from the drain. Also your bias arrangement is so far off for what is needed too. By using a P channel MOSFET as a source follower you need to reference the input to the positive rail. This may not be apparent immediately but is important when noise on power rails is considered.

Here's an P channel MOSFET common drain circuit i.e. source follower aka voltage follower: -

schematic

simulate this circuit – Schematic created using CircuitLab

R2 and R3 set the bias point to put the source roughly about half the supply rail. You would inject an AC signal into the gate via a capacitor to avoid upsetting the bias point.

If you are still intent on having your output from the drain then experiment with my circuit by putting a 1k resistor in the drain - keep the 100 ohm in the source though because this will stabilize and linearize the output.

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