# Identifier not declared in generic map, vhdl

Following a previous suggestion in this post i tried to write by my self an example, but it doesn't work.

Top entity

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;

entity topEntity is
generic(m : natural);
port(x : in std_logic_vector(m - 1 downto 0));
end topEntity;

architecture rtl of topEntity is
component componentEntity is
generic(n : natural);
port(x : in std_logic_vector(n - 1 downto 0));
end component;
begin
INSTANCE : componentEntity
generic map(n => m)
port map(x(n - 1) => '0', x(n - 2 downto 0) => x(m - 2 downto 0));
end architecture rtl;


Component entity

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;

entity componentEntity is
generic(n : natural);
port(x : in std_logic_vector(n - 1 downto 0));
end entity;

architecture foo of componentEntity is
begin
end architecture foo;


when i run ncvhdl -v93 it says:

ncvhdl: 15.10-s008: (c) Copyright 1995-2015 Cadence Design Systems, Inc.
port map(x(n - 1) => '0', x(n - 2 downto 0) => x(m - 2 downto 0));
|
ncvhdl_p: *E,IDENTU (topEntity.vhd,19|13): identifier (N) is not declared [10.3].


why it's not declared? it's a generic parameter properly initialized.

Update:

I putted: port map(x(m - 1) => '0', x(m - 2 downto 0) => x(m - 2 downto 0));

The result is

ncvhdl: 15.10-s008: (c) Copyright 1995-2015 Cadence Design Systems, Inc.
port map(x(m - 1) => '0', x(m - 2 downto 0) => x(m - 2 downto 0));
|
ncvhdl_p: *E,FMLNLS (topEntity.vhd,19|12): formal must be identified a locally static name 87[4.3.3.2] 93[4.3.2.2].
port map(x(m - 1) => '0', x(m - 2 downto 0) => x(m - 2 downto 0));
|
ncvhdl_p: *E,FMLNLS (topEntity.vhd,19|29): formal must be identified a locally static name 87[4.3.3.2] 93[4.3.2.2].
port map(x(m - 1) => '0', x(m - 2 downto 0) => x(m - 2 downto 0));
|
ncvhdl_p: *E,UFPTID (topEntity.vhd,19|29): port (X) must be associated [1.1.1.2].


Updated 2...

Still trying to figure out what it is the problem with all these kind of declaration/mapping in vhdl... my new attempt is:

The error report that formal must be identified a locally static name

I found a glossary where each term of interest for this error is explained it also refers to the language standard:

 locally static name: A name in which every expression is locally static (if every discrete range that appears as part of the name denotes a locally static range or subtype and if no prefix within the name is either an object or value of an access type or a function call). (§6.1)

locally static expression: An expression that can be evaluated during the analysis of the design unit in which it appears. (§7.4, §7.4.1)

analysis: The syntactic and semantic analysis of source code in a VHDL design file and the insertion of intermediate form representations of design units into a design library. (§1 1.1, §11.2, §11.4)


There's also the error with the port (X) must be associated

So i guess the problem could be that the name of the top entity input is x which is the same name as the component input. However i'm not sure about this because in general with port mapping like x => x don't cause any trouble to me...

Looking at the standard as static name it spits out that:

A name is said to be a static name if and only if one of the following conditions holds: — The name is a simple name or selected name (including those that are expanded names) that does not denote a function call, an object or value of an access type, or an object of a protected type and (in the case of a selected name) whose prefix is a static name. — The name is an indexed name whose prefix is a static name, and every expression that appears as part of the name is a static expression. — The name is a slice name whose prefix is a static name and whose discrete range is a static discrete range.

Futhermore a specification is given for locally static name, which should help me to figure out the problem with the name:

a name is said to be a locally static name if and only if one of the following conditions hold: — The name is a simple name or selected name (including those that are expanded names) that is not an alias and that does not denote a function call, an object or value of an access type, or an object of a protected type and (in the case of a selected name) whose prefix is a locally static name. — The name is a simple name or selected name (including those that are expanded names) that is an alias, and that the aliased name given in the corresponding alias declaration (see 4.3.3) is a locally static name, and (in the case of a selected name) whose prefix is a locally static name. — The name is an indexed name whose prefix is a locally static name, and every expression that appears as part of the name is a locally static expression. — The name is a slice name whose prefix is a locally static name and whose discrete range is a locally static discrete range

So the issue should be that the name x doesn't fall in any of the categories listed, but why?

• The problem is the usage of n inx(n - 2 downto 0). You are trying to use generic n which is not declared within topEntity, but is only known inside the entity componentEntity and its architecture foo. – andrsmllr Nov 3 '15 at 12:57
• I don't understand, what i mean with "is not declared within topEntity" the generic is of the component and in theory it should be aware of "n", how to fix instead? should i declare some constant somewhere in the architecture preamble of topEntity? – user8469759 Nov 3 '15 at 12:59

Try to replace your component instantiation with this:

INSTANCE : componentEntity
generic map(n => m)
port map(x(m - 1) => '0', x(m - 2 downto 0) => x(m - 2 downto 0));


Since n is not declared inside topEntity you can't use it. Your misconception is that the named generic n of componentEntity should be directly visible inside the port assignments region (that is port map (...)). This is not the case.
Since m and n are going to hold the same value (due to n => m) you can just use m when doing port assignments.

• I did as you told me, a new error just came out, see the update. – user8469759 Nov 3 '15 at 13:08
• Oh ok. You could change the port assignment to port map( x => "0" & x(m-2 downto 0) );. – andrsmllr Nov 3 '15 at 13:21
• But what's the problem in the updated version? – user8469759 Nov 3 '15 at 13:25
• Your last statement doesn't work too (because the expression isn't a locally static name). Locally static name means that the name is a simple name, indexed name or selected name that does involves a static evaluation, locally means that the evaluation depends from the current entity. I had two problem in my code, the first was the wrong use of the generic, which wasn't visible as you pointed out, the second is the the parameter m depends from the top entity, so the expression is globally static instead of local. – user8469759 Nov 3 '15 at 14:32
• Since the problem arises with the port map, i solved by declaring a signal x_loc, with the desired mapping, and then port the x in componentEntity into x_loc, so i avoided the problem. I was hoping in something shorter... but it's fine. – user8469759 Nov 3 '15 at 14:33

First off the basis for the errors:

IEEE Std 1076-1993,4.3.2.2 Association lists, para 14:

A formal may be either an explicitly declared interface object or member (see Section 3) of such an interface object. In the former case,such a formal is said to be associated in whole. In the latter cases,named association must be used to associate the formal and actual; the subelements of such a formal are said to be associated individually. Furthermore, every scalar subelement of the explicitly declared interface object must be associated exactly once with an actual (or subelement thereof)in the same association list, and all such associations must appear in a contiguous sequence within that association list. Each association element that associates a slice or subelement (or slice thereof) of an interface object must identify the formal with a locally static name.

You'll find as damage says that n is not defined (and you'd expect a separate error message). You also don't define m, both of which need to have values declared for elaboration.

Neither generic is locally static:

7.4 Static expressions:

Certain expressions are said to be static. Similarly, certain discrete ranges are said to be static, and the type marks of certain subtypes are said to denote static subtypes.

There are two categories of static expression. Certain forms of expression can be evaluated during the analysis of the design unit in which they appear; such an expression is said to be locally static. Certain forms of expression can be evaluated as soon as the design hierarchy in which they appear is elaborated; such an expression is said to be globally static.

7.4.1 Locally static primaries:

An expression is said to be locally static if and only if every operator in the expression denotes an implicitly defined operator whose operands and result are scalar and if every primary in the expression is a locally static primary, where a locally static primary is defined to be one of the following:

a. A literal of any type other than type TIME
b. A constant (other than a deferred constant) explicitly declared by a constant declaration and initialized with a locally static expression ...

Generics are globally static:

7.4.2 Globally static primaries:

An expression is said to be globally static if and only if every operator in the expression denotes a pure function and every primary in the expression is a globally static primary, where a globally static primary is a primary that, if it denotes an object or a function, does not denote a dynamically elaborated named entity (see 12.5 ) and is one of the following:

a. A literal of type TIME
b. A locally static primary
c. A generic constant

An expression can be both globally static and locally static, a generic isn't one of those, it's value is fixed at elaboration time (even with a default value):

12.2.1 The generic clause:

Elaboration of a generic clause consists of the elaboration of each of the equivalent single generic declarations contained in the clause, in the order given. The elaboration of a generic declaration consists of elaborating the subtype indication and then creating a generic constant of that subtype.

The value of a generic constant is not defined until a subsequent generic map aspect is evaluated or, in the absence of a generic map aspect, until the default expression associated with the generic constant is evaluated to determine the value of the constant.

4.3.2.1 Interface lists, para 3:

A generic interface list consists entirely of interface constant declarations....

So a a generic is a constant. It's not a deferred constant in the meaning given in 4.3.1.1 Constant declarations, para 4:

If the assignment symbol ":=" followed by an expression is not present in a constant declaration, then the declaration declares a deferred constant. Such a constant declaration may only appear in a package declaration. The corresponding full constant declaration, which defines the value of the constant, must appear in the body of the package (see 2.6 ).

The lack of a defined value will cause an elaboration error:

1.1.1.1 Generics, para 3:

The value of a generic constant may be specified by the corresponding actual in a generic association list. If no such actual is specified for a given formal generic (either because the formal generic is unassociated or because the actual is open), and if a default expression is specified for that generic, the value of this expression is the value of the generic. It is an error if no actual is specified for a given formal generic and no default expression is present in the corresponding interface element. ...

And also tells us we can supply the value in an association list (which your code example doesn't do).

And about now you can get the idea that VHDL is pretty complex. Mastery follows a journeyman system, albeit with the road to mastery taking longer than 3 years and there's no investiture by your fellows at the end and the board of masters are those producing VHDL tools (and they agree on what is the standard).

I liken it to someone studying religious texts. Almost all your answers can be found in the LRM (The first sentence of the introduction to the standard "The VHSIC Hardware Description Language (VHDL) is a formal notation intended for use in all phases of the creation of electronic systems. ", a formal notation has to be formally defined). It's a matter of how well you know the standard, how inculcated you can be with the terminology or how well you can search the standard. And the latter two aren't emphasized in educational institutes 'teaching' VHDL. You actually teach yourself.

On the other hand tool vendors could do a lot better at providing information on errors, potentially avoiding the need for mastery to make sense of an issue.

And the good news is that while analyzing your last two questions I've found and submitted two bugs found in my favorite VHDL tool. (In case you're wondering what would possess someone to analyze questions in depth).