# Output of XOR gate with high-impedance input

One of the exercises in university was to output a truth table for the gate, which takes an input

t, and returns

t ^ t, where ^ is a xor gate.

Now if t = 1 or t = 0, the output is always 0. Furthermore, even if the input is t = X (don't know), the output is still 0.

What I am not sure is the answer in case an input is Z (high impedance).

My guess would be that the output is also Z, because the output wire is not driven by anything. Could anyone confirm / deny this?

Also, any other examples using other gates (such as AND / OR) and Z values would be appreciated.

To answer your actual question, no, the output of a gate is never "Z", unless it's specifically designed as a tristate gate with an output enable.

In general, inputs to gates that are "Z" are treated the same as "X", and the output is either "0", "1" or "X" as appropriate.

For the specific case of the XOR with its inputs tied together, your original statement that input "X" gives output "0" is correct — although many simple-minded logic simulators get this wrong. The problem is that they can't distinguish between two inputs being the same unknown value versus two independent unknown values.

Now if t = 1 or t = 0, the output is always 0. Furthermore, even if the input is t = X (don't know), the output is still 0.

This is incorrect. If you don't know what the input to a gate is, you certainly don't know its output! If either input is X, the output should be X as well.

Anyways, the behavior of a logic gate when given a high-impedance (floating) input is undefined. Depending on the specific circuit and the logic family in use, the input may float high or low, remain at its most recent defined level, or even oscillate. None of these behaviors will be reliable, and the best answer is probably "don't do that". :)

From a perspective of Verilog values, though, the correct answer here is probably just "unknown" again (X).

• Not sure if you understood the question (or maybe I'm misunderstanding!), but I believe the OP's assertion is correct. Based on the description, the logic gate is an XOR with a single input that XOR's the input to itself. So matter what the input is, the output is always 0. – Dan Laks Nov 4 '15 at 8:19
• I disagree, with input t = X. X means "don't know", but it is a fixed value. That to say, it's EITHER 1 OR 0, just one does not know which. Now if x = 1, then x^x = 0, if x = 0, then also x^x = 0. So in both cases x^x = 0. – mercury0114 Nov 4 '15 at 8:46
• X doesn't just mean "either high or low", though. It can also include ill-defined states, such as the result of wire-ORing high and low together, or performing logic on a floating value. XORing such a value with itself wouldn't give you a "clean", well-defined output. – duskwuff Nov 4 '15 at 8:53
• So what's the ill-defined state then, and how X differs from Z? My understanding is that each signal has some voltage V in the range of [0, V_max]. Now if V ~ 0, then the signal is said to be "0", if V~V_max signal is said to be "1", if V is somewhere in the middle, then signal is said to be "Z". Is that wrong? BTW, it's not always true that if an input is not known, the output is also not known. Consider t AND 0. The output is 0 regardless of what t is, even it t = X or t = Z. At least that's written in the course notes, what's called "four value logic" to simulate circuit in SysVerilog. – mercury0114 Nov 4 '15 at 9:07

The "Don't Care" or "X" state applies only to inputs and is used to indicate that the output of the circuit won't change, regardless of the state of the X input.

For example, consider an AND with one input low, and it becomes apparent that no matter how many other inputs there are to the gate, they'll all be "Don't Cares" because the output will stay low no matter what states the X inputs take.

The same is true of an OR with any input high, since the output will stay high regardless of the states of the X inputs.

The "Z" almost always refers to outputs which have been placed in a high-impedance or "floating" state in order to ,for example, relinquish control of a bus in order to share resources in an economical way.

If used to describe an input, it almost certainly refers to an input which has been allowed to float, which is disallowed or, at best, frowned upon.

• During simulation:

"t XOR t" gives an answer x when t is assigned to x. This becomes apparent by the following observation that

a XOR b


is equivalent to

(a and !b) or (!a and b)


The truth tables of four logic system (in SystemVerilog language) are such that

not x = x
x and x = x
x or x = x


from which one can deduce the value of "t XOR t" by binding a and b to t.

The same happens with z value: "z XOR z = x"

(In simulation x is referred as don't care.)

• On real hardware

The synthesizer produces the actual XOR gate. X as a value no longer exists and is replaced by either 0 or 1. Although one can not be sure which of the two values is used, the output of a XOR gate will certainly be zero. One can see that from the example:

reg [9 : 0] ten_values;
assign ten_values = 10'b00_11_xx_zz_xz;
assign LEDR = (ten_values ^ ten_values) ^ 10'b11_11_11_11_11;


This is the code to program de1_soc (an FPGA which also contains 10 LEDS). I-th LED is supposed to turn on if and only if LEDR[i] is high. After downloading compiled code to FPGA the result was that all leds were on. Hence, this shows, that input XOR-ed with itself always gives 0 regardless of its value.

(After synthesis x is referred as don't know.

Once the circuit design is complete and a real circuit is
constructed, the "X" values will no longer exist. They will become
some tangible "0" or "1" value but could be either
depending on the final design optimisation.


Paragraph from Wikipedia https://en.wikipedia.org/wiki/Four-valued_logic)

Conclusion: results during simulation (x XOR x = x) can differ from results on an actual chip (x XOR x = 0 if both x come from the same source).