# Constraint relative arrival time for a group of signals

Imagine a situation where the absolut delay of a group of signals doesn't matter, but it must be ensured each signal of the group has roughly the same delay until it reaches a certain point, say a FF. How does the constraint for this look like?
E.g. there are 4 signals (A-D) arriving from outside the FPGA. I don't care how long these signals are delayed inside the FPGA, as long as they arrive at the FFs within a time window of +/- X ns, i.e. A arrives at a FF at time T, D arrives at a FF at time T+X ns, and B and C arrive at FFs some time in between.
Is it possible to formulate a fitting constraint in Xilinx' UCF or XCF syntax? Or do all these timings have to be handled within the IOBs and there is no way to handle this inside the FPGA?
The desired constraint seems to be similar to an OFFSET constraint, but is not the same, since there is no maximum value for the total delay.

• Do you use I/O-FFs in the IOB? If so, the delay is fixed because the path on PCB and in the FPGA from pin to I-FF are known. – Paebbels Nov 4 '15 at 20:05
• If I understand this right, you want to make sure that all the signals from an outside source arrive at the same time to the internal FF of the FPGA. This is can be done in many different way. If you have access to the information form the board to know roughly how much the differnce is the delay between each signals based on the routing, you may add a idelay for the signals to compensate for the delay of the PCB. – FarhadA Nov 6 '15 at 12:27

TIMEPSEC "TS_PAD2FF" = FROM PADS("my_ports") TO FFS("my_ffs") 4 ns;