I am referring to the following AppNote from TI. What is the purpose of transistors Q3 and Q2? Is it to turn the PFET "hard off" when the controller isn't turning it on?

Circuit Image

Thanks AJ


I'm not sure, but it seems they are used to switch off Q1 quickly. Follow my reasoning and see if it makes sense to you.

First of all you should consult the datasheet for the controller chip BQ2031. It describes the chip operations and tells that its MOD pin is the PWM output that allows to control the charging cycle through (ultimately) Q1.

At page 10 you'll see the formula for the frequency of operation, that will depend on the value of C12 (see full schematic in the app-note): 1000pF=1nF sets the frequency at 100kHz, i.e. a period of 10us. This is important because at that frequency C4 can be considered a short circuit: in fact when MOD is LOW and Q4+Q5 are off C4 charges through R4, Q2's base, R6 and R21 (then we reach the output which is at ground for the signal): a total of ~40kOhm. This makes an RC time constant of C4 x 40kOhm = ~ 40us, much longer than the PWM period (the discharge follows a different path, but the resistance seen by C4 is similar).

Therefore we can consider C4 a short for the PWM signal. So we can see that Q2 and Q3 have a complementary function relative to Q4+Q5: these latter turn Q1 on by switching its gate to ground, whereas Q2+Q3 turn Q1 off by switching its gate to "+" (and discharging its gate capacitance quickly).

The fact that Q2 and Q3 have the same part numbers as Q5 and Q4 (respectively) can be seen as a clue of their complementary action.

  • \$\begingroup\$ Thanks for the detailed explanation, I was on the right track, for the most part! D2 is a 15V Zener, does that mean that the minimum voltage applied to the Gate of Q1 would be 15V? I want to implement this charger in an application that accepts up to 48V DC on VIN. Most FETs can only tolerate +-20V for Gate to Source. \$\endgroup\$ – AJBotha Nov 6 '15 at 6:19
  • \$\begingroup\$ According to MTP23P06V datasheet Vgs is limited to +-15V (continuous), so probably that Zener is there to prevent damage to Q1 in case of some spikes. Using that circuit up to 48V entails some overall redesign most probably. \$\endgroup\$ – Lorenzo Donati supports Monica Nov 6 '15 at 11:12
  • \$\begingroup\$ Thank you for the help. Looks like I have some gate driver circuit research to do! \$\endgroup\$ – AJBotha Nov 6 '15 at 11:19

Collectively the network of Q2, Q3, Q4, Q5, R4, R6, R7, R8, R22, C4 and D2 are what you would call a gate-drive circuit. The purpose of such a circuit is evident in its name; in this case it is to switch the PFET Q1 by controlling the charging and discharging of its gate-source capacitance. Both Q2/Q3 and Q4/Q5 are wired as a Sziklai Pair in order to achieve a higher current gain. (The higher the current sourcing and sinking capability the faster you can charge and discharge the Cgs of the FET.)

The Q4/Q5 pair acts to turn on the FET (charges Cgs), and Q2/Q3 act to turn off the FET (discharges Cgs).

  • \$\begingroup\$ Thank you for pointing out the circuit name, that certainly makes research easier. Can you perhaps check out my comment on @LorenzoDonati post regarding the allowable voltages? \$\endgroup\$ – AJBotha Nov 6 '15 at 6:25
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    \$\begingroup\$ Well ... Q2/Q3 are actually Sziklai pairs. As are Q4/Q5, although not as topologically pure an example. \$\endgroup\$ – gsills Nov 8 '15 at 1:27
  • \$\begingroup\$ Thanks for the correction, I had never encountered that term before. \$\endgroup\$ – ConduitForSale Nov 8 '15 at 13:03
  • \$\begingroup\$ Very interesting, I have never seen that before. Thanks! @gsills \$\endgroup\$ – AJBotha Nov 9 '15 at 5:57
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    \$\begingroup\$ Just for the record: "...charging and discharging of its gate-source junction..." Q1 is not a JFET nor a BJT, but a P-channel MOSFET, so it has no gate-source junction. You probably meant "capacitance" instead. \$\endgroup\$ – Lorenzo Donati supports Monica Dec 6 '15 at 22:37

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