Why Increasing Collector Voltage Reduces Collector-base Capacitance

Question

I'm looking at some transistor radio circuits and the book I'm following makes the following statement with regard to AC gain: "By raising the DC voltage at the collector, the internal collector-base capacitances of the transistor are reduced".

Here's a circuit to help understand what's going on:

Here the author has killed the DC gain by placing an inductor in parallel with R2 whilst leaving the AC gain intact: collector reactance (L1||R2) / emitter reactance (C3||R3).

I have a reasonable grasp of the effect of Miller Capacitance on an inverting amplifier, where the inverted output acts negatively on the input. What I don't understand is why increasing the collector voltage acts to reduce collector-base capacitance.

Does the increase in current flowing through the collector-emitter junction have anything to do with it?

Answer 1

As @FakeMoustache hinted in a comment to your question, the explanation lies in the behavior of a reverse-biased PN junction, because that's what Q1's collector-base junction is in your circuit.

From a macroscopic point of view any reverse-biased PN junction acts like a parallel-plate capacitor whose capacitance (called transition capacitance \$C_T\$) depends inversely on the reverse voltage \$V_R\$. The relationship is not linear, but it is approximately:

$$ C_T = K \dfrac{1}{\sqrt{V_0 + V_R}} $$

where \$V_0\$ is the voltage gap created by the junction and \$K\$ is a constant.

EDIT

Struggling to remember the exact form of the formula (there are half a dozen of ways of writing down that relationship, depending on which physical parameters of the junction you want to emphasize) I found a more intuitive formula in this Google book:

$$ C_T = \dfrac{C_0}{(1 + V_R)^n} $$

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^{Note: That formula has an error in it (dimensional analysis debunks it). Probably \$V_R\$ is meant to be the relative voltage with respect to some reference. I guess the correct formula should be: $$ C_T = \dfrac{C_0}{\left(1 + \dfrac{V_R}{V_0}\right)^n} $$}

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where \$C_0\$ is the capacitance when no bias is applied and \$n\$ depends on how the junction is doped: \$n = \frac 1 2\$ for step-graded junctions, whereas \$n=\frac 1 3 \$ for linearly-graded junctions.

Another interesting article on the subject (tougher semiconductor physics stuff) explains how to derive that relationship (in yet another form!).