Could someone please explain the difference between full address decoding and partial address decoding?

I am reading the chapter on digital logic in "Structured Computer Organization", 6th ed. by Tanenbaum, but I don't think address decoding is explained very well. The book says that the address decoding logic of figure A is full address decoding. And that of figure B is partial because "the full addresses are not used". I don't understand that. To me, it seems like full addresses are not used in figure A either? enter image description here enter image description here

  • \$\begingroup\$ Looks like on A the two lower bits of the address are not used, unless you are not giving all of the information. They can be used elsewhere \$\endgroup\$
    – Eugene Sh.
    Nov 5, 2015 at 17:23

2 Answers 2


Memories and peripheral IC's will typically have many locations that can be selected for reading or writing; in the example above, the 2K devices (EPROM and RAM) containing 2\$^{11}\$ (2048) memory cells require 11 address bits A0 thru A10. These are fed directly into the chip and are internally decoded to select the desired memory location or register. These address lines are not shown in the partial schematics above.

Computer boards with external memory and peripherals connected to the processor may have several chips that need to be addressed. Only one can be connected to the data bus of the computer at a time. Which one is enabled is done via a chip select (CS) line. These lines are normally inverted; i.e. the chip is enabled if the line is low (logic 0), and disabled when the line is high (logic 1). So they are written as \$\small \overline{\text{CS}}\$ to indicate this.

With full address decoding, all the bits of the address bus that are not used to address the internal locations mentioned above are decoded to select a particular chip via its CS line. So for a 16-bit address bus (64K memory map), five lines (A11 thru A15) will be used for the chip select decode and the remaining 11 (A0 thru A10) used for the address bus fed into the chip. The chip will respond to only as many addresses as there are internal memory locations inside the chip. So for example, a 2K memory chip may have addresses 0x0000 thru 0x7FFF (2048 altogether) or some other 2K range; any addresses outside of the 2K addresses will have no effect.

With partial address decoding, some of the address lines which would normally be used to enable the chip select line are left unconnected as far as the address decoding goes; these are called "don't cares". Each line that is specified as a don't care doubles the number of addresses that can select the chip. For example, if A11 was left out of the decoding for the EPROM, it would still respond to address 0x0000 thru 0x07FF, but it would also respond to addresses 0x0800 thru 0x0FFF. So 0x0123 and 0x0923 would address the same internal location.

Why use partial address decoding? It sometimes saves some logic gates. That's really the only reason. In the example (a) above, the full addressed example (a) required a NOR gate and an inverter for the EPROM; in the second example (b) no logic was required. However partial address decoding is usually a bad idea since it wastes space in your memory map.

The top example (a) is fully decoded; the decoding look like this:

           A15 14 13 12   11 10  9  8    7  6  5  4    3  2  1  0

 2Kx8 EPROM  0  0  0  0    0  A  A  A    A  A  A  A    A  A  A  A 

 2x8K RAM    1  0  0  0    0  A  A  A    A  A  A  A    A  A  A  A 

 PIO         1  1  1  1    1  1  1  1    1  1  1  1    1  1  A  A

The A's indicate decoding external to the CS lines, and are address bits in the case of the EPROM and RAM, or assumed to be register selects in the case of the PIO device.

The 2K devices (EPROM and RAM) require 11 address bits A0 thru A10. The top five bits A11 thru A15 are fully decoded to enable the CS lines. So the address range of the EPROM is 0x0000 thru 0x07FF. The address range of the RAM is 0x8000 thru 0x87FF.

The PIO CS is selected when bits A2 thru A15 are high. So the address range is just 0xFFFC thru 0xFFFF.

Looking at the logic equations, where \$\cdot\$ = AND, + = OR, and overbar = NOT:

\$\small CS_{EPROM}= \overline{\small A_{15}+A_{14}+A_{13}+A_{12}+A_{11}}\$ which by De Morgan's laws is the same as:

\$\small CS_{EPROM}=\overline{\small {A_{15}}}\cdot\overline{\small {A_{14}}}\cdot\overline{\small {A_{13}}}\cdot\overline{\small {A_{12}}}\cdot\overline{\small {A_{11}}}\,\,\$(i.e. CS enabled when \$\small A_{15}\$ thru \$\small A_{11}\$ are all low).

Although using a NOR to do an AND'ing function looks odd, doing it this way saved four inverters (NOR and one inverter instead of five inverters and a NAND). But they could have used an OR instead of the NOR and gotten rid of the inverter.

\$\small CS_{RAM}\,\,\,\,\,=\overline{\small \overline{A_{15}}+A_{14}+A_{13}+A_{12}+A_{11}}\$ which is the same as:

\$\small CS_{RAM}\,\,\,\,\,=\small {A_{15}}\cdot\overline{\small {A_{14}}}\cdot\overline{\small {A_{13}}}\cdot\overline{\small {A_{12}}}\cdot\overline{\small {A_{11}}}\,\,\$(i.e. CS enabled when \$\small A_{15}\$ is high and \$\small A_{14}\$ thru \$\small A_{11}\$ are all low).

Doing it this way saved three inverters (NOR and two inverters instead of five inverters and a NAND). But they could have used an OR instead of the NOR and gotten rid of one of the two inverters.

\$\small CS_{PIO}\,\,\,\,\,\,\,=\small \overline{\overline{A_{15}\cdot A_{14}\cdot A_{13}\cdot A_{12}\cdot A_{11}\cdot A_{10}\cdot A_{9}\cdot A_{8}} + \overline{A_{7}\cdot A_{6}\cdot A_{5}\cdot A_{4}\cdot A_{3}\cdot A_{2}}}\$ which is the same as:

\$\small CS_{PIO}\,\,\,\,\,\,\,=\small A_{15}\cdot A_{14}\cdot A_{13}\cdot A_{12}\cdot A_{11}\cdot A_{10}\cdot A_{9}\cdot A_{8}\cdot A_{7}\cdot A_{6}\cdot A_{5}\cdot A_{4}\cdot A_{3}\cdot A_{2}\,\,\$ (i.e. CS enabled when \$\small A_{15}\$ thru \$\small A_{2}\$ are all high).

In the last case, I don't know why they didn't use two AND gates and a NAND, instead of the two NAND gates and an OR; the first would have been more straightforward.

The bottom example (b) is partially decoded; the decoding looks like this (where the x's indicate "don't care" lines -- note the top example has no x's, that's why it is considered fully decoded):

           A15 14 13 12   11 10  9  8    7  6  5  4    3  2  1  0

 2Kx8 EPROM  0  x  x  x    x  A  A  A    A  A  A  A    A  A  A  A 

 2x8K RAM    1  0  x  x    x  A  A  A    A  A  A  A    A  A  A  A 

 PIO         1  1  x  x    x  x  x  x    x  x  x  x    x  x  A  A

Once again The 2K devices (EPROM and RAM) require 11 address bits A0 thru A10. Only the top bit is used to enable the CS line of the EPROM, and the top two bits are used to select the CS lines of the RAM and PIO.

Due to the partial decoding, the EPROM can be addressed using the following ranges 0x0000 thru 0x7FFF, or broken up into 2K blocks,

0x0000 thru 0x07FF, 0x0800 thru 0x0FFF, 0x1000 thru 0x17FF, 0x1800 thru 0x1FFF, 0x2000 thru 0x27FF, 0x2800 thru 0x2FFF, 0x3000 thru 0x37FF, 0x3800 thru 0x3FFF, 0x4000 thru 0x47FF, 0x4800 thru 0x4FFF, 0x5000 thru 0x57FF, 0x5800 thru 0x5FFF, 0x6000 thru 0x67FF, 0x6800 thru 0x6FFF, 0x7000 thru 0x77FF, 0x7800 thru 0x7FFF

The RAM is almost the same, except the high bit A15 is 1 and A14 is 0. (A14 differentiates the RAM from the PIO, which also has the high bit set.) It can be addressed using the following ranges 0x8000 thru 0xBFFF, or broken up into 2K blocks,

0x8000 thru 0x87FF, 0x8800 thru 0x8FFF, 0x9000 thru 0x97FF, 0x9800 thru 0x9FFF, 0xA000 thru 0xA7FF, 0xA800 thru 0xAFFF, 0xB000 thru 0xB7FF, 0xB800 thru 0xBFFF

The PIO chip is addressed with the top two address bits high. Assuming the PIO still has only two bits of register addressing, A0 and A1, then bits A2 thru A13 are not decoded, allowing a range of 0xC000 thru 0xFFFF. I'm not going to write out all of the ranges (they're 4096 of them), but they start out as 0xC000 thru 0xC003, and the last range is 0xFFFC thru 0xFFFF.

Looking at the logic equations,

\$\small CS_{EPROM}=\overline{\small {A_{15}}}\,\,\,\,\,\,\$(i.e. CS enabled when \$\small A_{15}\$ is low).

\$\small CS_{RAM}\,\,\,\,\,=\small A_{15}\cdot\overline{\small {A_{14}}}\,\,\$(i.e. CS enabled when \$\small A_{15}\$ is high and \$\small A_{14}\$ is low).

\$\small CS_{PIO}\,\,\,\,\,\,\,=\small A_{15}\cdot A_{14}\,\,\$(i.e. CS enabled when \$\small A_{15}\$ and \$\small A_{14}\$ are both high).

  • \$\begingroup\$ So the difference is that partial decoding has "don't care" lines, and full decoding doesn't? But what I still don't understand is: in figure A, how is a particular address in, for example, the EPROM selected, when the 11 lower lines are not connected? I understand that EPROM is selected as long as A15-A11 are 00000, but how would I select a specific address in the EPROM? \$\endgroup\$ Nov 6, 2015 at 8:35
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    \$\begingroup\$ @AliMustafa In each of these partial schematics, they just show the decoding for the address lines that enable the CS (chip select) inputs. The remaining address lines (e.g. A0 thru A10 for the EPROM and RAM) would be connected directly to the chip, which is not shown. Granted, a little confusing. The decoding for these additional lines (i.e. which of the 2048 locations is selected) is done internally in the EPROM or RAM. \$\endgroup\$
    – tcrosley
    Nov 6, 2015 at 8:40
  • \$\begingroup\$ Thank you, it is clearer to me now. But one last question, in partial decoding, would 0111 1000 0000 0000, 0101 0000 0000 0000 and 0000 0000 0000 0000 all select the same address in the EPROM? Since A14-A11 don't matter? \$\endgroup\$ Nov 6, 2015 at 8:51
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    \$\begingroup\$ @AliMustafa Yes your example is correct. Note I included those three addresses as the beginning of three equivalent ranges in my answer (0x0000 thru 0x07FF, 0x5000 thru 0x57FF, 0x7800 thru 0x7FFF). Also note, I added five more paragraphs to the beginning of my answer based on your earlier questions. \$\endgroup\$
    – tcrosley
    Nov 6, 2015 at 9:13
  • \$\begingroup\$ (+1) Excellent answer with real effort! I just found some more time to expand my answer, but I found yours. You saved me quite some time ;-) \$\endgroup\$ Nov 6, 2015 at 10:52

In figure (a) the part of the address bus that addresses the locations/registers inside the individual chips is not shown. For example the first two memory banks have 8K(=8192=2^11) locations that must be addressed using the lower 11bits of the address bus (not shown connected) they only show the decoding network for the chip select pin (/CS).

Again, the PIO /CS pin is decoded using the highest 14 address lines, the lowest two (not shown) are probably used to address the internal registers of the chip (which would be 4=2^2 independent register).

Therefore full address decoding is indeed performed: the full address bus is used to address a location/register in the peripheral. The lines that are not used for chip selection are used to address inside the peripheral.

In figure (b) only some lines of the higher part of the address bus are used to select the chips, so the chips will be accessible at different locations of the address space. For example a single location inside the EPROM will be accessible using different addresses (any address which has the A15 line low).

In other words, the difference between the two addressing strategies is the following: with full decoding a single location/register in the external chip will be visible at only one address in the physical address space, whereas with partial decoding it will be "aliased" to multiple addresses.

Partial decoding is simpler (i.e. hardware-wise, especially for wide buses), but can cause management problems at higher level (e.g. in software you must pay attention not to select multiple chips when asserting a given address on the bus if the chips cannot handle it).

  • \$\begingroup\$ Thank you for the answer, but I still don't understand two things: 1) if you don't see the text underneath the picture saying which uses full addressing and which doesn't, how can you tell by the pictures? 2) why can I access EPROM with, for example, 0111 1111 1111 1111 when it's only supposed to be addresses 0 to 2kB? \$\endgroup\$ Nov 5, 2015 at 17:59
  • \$\begingroup\$ I don't have a copy of that book, so I can't tell how the explanation goes, but you are right in saying that you cannot tell by the figures alone. But in a real design the system designer does know and the system user (at assembly level) will know. As I said, in the partial decoding, the internal addresses of the EPROM are aliased at different bus addresses. Think of it as different names for the same person. \$\endgroup\$ Nov 5, 2015 at 18:08
  • \$\begingroup\$ you can so tell by just the figures alone in Fig 3-61 (b). \$\bar{CS}\$ is active low. independent of the other 15 lines, whenever A15 is 0, the 2K-word EPROM is selected. the number of addresses that select the 2K-word EPROM is 32K but there are only 2K different locations in the 2K-word EPROM. each of those locations have 16 different addresses that go there. that means 4 \$ = \log_2(16)\$ address lines (A11 to A14) are not decoded by anything in the EPROM. they are "don't care" bits. for the other two devices A15 must be 1, and the selection of one of those 2 devices is by A14 only. \$\endgroup\$ Nov 6, 2015 at 2:57

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