This is a short question but a seemingly important one.

Is it possible for a multi-master i2c bus to have two masters send the start byte at almost exactly the same time?

If so, what would happen?


It is perfectly possible for two masters to send a start bit at exactly the same time, where with exactly I mean that the difference between the start bits falling fronts is smaller than the smaller measurable difference by the masters.

That's the point: when a master is writing on the i2c bus it is also monitoring it, thus it is possible to determine if a collision is occurring.

Let's say that two masters, A and B, connected to the same bus, want to address two different devices, one with address 0xAE (from A), the other with address 0xA6 (from B). The masters send the start bit at almost the same time, then begin sending the address. Since 0xA = 0b1010 they send the sequence 1010, so far so good, but 0xE = 0b1110, while 0x6 = 0b0110. The fifth bit differs, and A tries to send a 1, while B sends a 0.

Who wins? B of course, because i2c is an open collector bus, lines can only be tied low. To send a 1 you just turn off the output and an external pull up resistor ties the line high, while to send a 0 you turn on a pull down. Master A then is sending a 1, but measuring a 0. Big red flag, bus collision! Master A state machine should properly handle the situation, leaving the bus to B.

Please note that from B point of view nothing has happened, and it continues happily with the frame. That is very good because no time is lost and B can do whatever it needs to do.

While it seems that an open collector bus is the solution to all the problems, unfortunately it is not so. The bus can easily be blocked by any malfunctioning device that decides to hold SCL or SDA low. In such situations it is very difficult to reset the bus, sometimes devices have a reset pin, sometimes you have to power cycle them, sometimes you have to think of something even different. Had to do all the three in different applications.

As a side note be aware that not all masters implement the full spec, some masters do not implement bus collision detection and this can be very bad. In the previous example, if nor A nor B can detect loss of arbitration the address sent on the bus is 0b10100110, i.e. B slave address, but when the ACK comes A thinks it comes from its slave, and after that things can get very bad.

There also is the possibility that A and B wants the same slave. If this happens the ACK is received, and then many things can happen.

Usually i2c devices have many registers that can be written and/or read, the communication frame then looks something like:

slave address; ACK; reg address; data;

(Omitting start and stop bits and WR bit).

The masters start sending the register address. If they want to access a different register it just happens what would happen for the slave address: at a certain point one of them detects the loss of arbitration and gives up.

If the masters want to access the same register, or the i2c device has a default behaviour like "if I detect my address I'll tell you the temperature", then... Everything is perfectly fine! Both masters wanted exactly the same thing, and they are getting it, and this is OK per the standard.

Two communications in only one frame, take that Nyquist!

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    \$\begingroup\$ What if a and b both want the same slave \$\endgroup\$
    – Passerby
    Nov 5 '15 at 19:03
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    \$\begingroup\$ oook, I'll add that. \$\endgroup\$ Nov 5 '15 at 19:04
  • \$\begingroup\$ @Passerby If a and b both want the same slave, it's no different from wanting a different slave. They keep going until one tries to send a 0 while the other tries to send a 1. Whoever sends the 0 wins. They can also monitor the SCL line to see if there is a collision - it one is trying to drive the clock high while the other is driving it low, the one driving high knows there is a collision. \$\endgroup\$ Nov 5 '15 at 21:27
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    \$\begingroup\$ @tomcarpenter that sounds like clock stretching not being supported then \$\endgroup\$
    – Passerby
    Nov 5 '15 at 21:55
  • \$\begingroup\$ exactly. I'm not sure a "clock is still low" would be ever interpreted as arbitration loss, because clock is still low is okay and is clock stretching \$\endgroup\$ Nov 5 '15 at 22:36

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