2
\$\begingroup\$

I was wondering if there is a difference between (two potential implementations of a counter in verilog with a case statement...

module counter_4(
    input clock;
    output reg[3:0] count;
    );
    always @(posedge clock) begin
        case(count)
            0: count = 1;
            1: count = 2;
            2: count = 3;
            3: count = 4;
            4: count = 5;
            5: count = 6;
            6: count = 7;
            7: count = 8;
            8: count = 9;
            9: count = 10;
            10: count = 11;
            11: count = 12;
            12: count = 13;
            13: count = 14;
            14: count = 15;
            15: count = 0;
        endcase
    end
endmodule

or with an increment...

module counter_4(
        input clock;
        output reg[3:0] count;
        );

    always @(posedge clock) begin
        count = count+1;
    end
endmodule

These may not even be working code, I don't have access to a compiler right now, but hopefully it's enough to get the idea across. Why (aside from the brevity of the increment code) would I use one method or another?

\$\endgroup\$
  • \$\begingroup\$ I love downvotes without explanations. They are super helpful. \$\endgroup\$ – Daniel B. Nov 6 '15 at 1:40
  • \$\begingroup\$ At some stage (been a while) DC would implement +/- as a ripple carry unless you specified otherwise. (+1 without explanation :-).) \$\endgroup\$ – copper.hat Nov 6 '15 at 4:52
3
\$\begingroup\$

The two codes produce identical output, so it's down to your synthesis tool whether they produce the same implementation.

With the first one, the synthesis tool may be more likely to co-optimize the logic to produce the 4 output bits.

With the second one, the synthesis tool may be more likely to use special-purpose hardware (like fast carry chains in FPGAs).

But in principle, either code could be implemented with any logic that produces the correct outputs.

If you really need to know which one produces better results (depending what you consider better), you need to try both on your synthesis tool and compare the results. I think it's quite likely that for an FPGA implementation on current FPGAs, you get the same result (one LUT and one flip-flop per output bit) with either code.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.