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I am using IDT 85104 Buffer IC for clock distribution in my design. I need to give the clock output of this Buffer to a device @ 156.25 MHz. I have 2 doubts :-

1. In the parameter table of 85104, it is given that Absolute max output voltage is 1150 mV (with a Note - measurement taken from single ended waveform). What is the meaning of Absolute max output voltage of a diff signal and the Note??

2. I am providing this clock to an IC which says Max input voltage is 1V. What is the problem I am going to get here!!.

The clock output of 85104 is HCSL 0.7V.

Please tell me if I should provide additional information.

Datasheet of Input Device can be downloaded from here :-

http://www.idt.com/products/interface-connectivity/pci-express-solutions/pci-express-serial-rapidio-bridges/tsi721-rapidio-bridge

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    \$\begingroup\$ 85104 is LVCOMS to HCSL fanout buffer and output level of HCSL is never 3.3V, please cross check the output voltage levels you are expecting. \$\endgroup\$ – AKR Nov 6 '15 at 4:44
  • \$\begingroup\$ It is 0.7V. By mistake wrote 3.3V. \$\endgroup\$ – Oshi Nov 6 '15 at 4:46
  • \$\begingroup\$ I hope your clock input to the 85104 is LVCMOS/LVTTL i.e. VIH is more than 2V and VIL is less than 0.8. Take care of the terminations suggested in the datasheet diagrams. It will do. \$\endgroup\$ – AKR Nov 6 '15 at 4:50
  • \$\begingroup\$ Can you provide the data sheet of the input device? \$\endgroup\$ – Paebbels Nov 6 '15 at 7:00
  • \$\begingroup\$ Datasheet Link added in post. \$\endgroup\$ – Oshi Nov 7 '15 at 4:16
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That is a very odd datasheet. Normally when we talk about "absolute maximum" ratings, we mean this table from page 4 in the datasheet:

enter image description here

These are requirements for how you must use the chip to avoid damaging it.

The spec you are referring to is in a table labelled "AC Characteristics". Normally a "characteristic" spec is a promise from the chipmaker about the behavior of the chip, not a requirement for how you should use the chip.

As I read it, they are promising that the output differential voltage will absolutely not exceed 1150 mV. A figure on page 8 tries to clarify what they mean by the spec:

enter image description here

I can't say how this relates to the requirements for your other chip without seeing the datasheet for the other chip.

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  • \$\begingroup\$ Datasheet Link added in post. \$\endgroup\$ – Oshi Nov 7 '15 at 4:16

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