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I'm busy learning about flip flops. It's my understanding that JK flip flops toggle when JK are both 1. However without a master slave arrangement this will lead to a race condition, so the master slave arrangement creates negative edge triggered behaviour that stabilizes the output. Makes sense.

I also understand that T flip flops are just JK flip flops with the same input to J and K. This makes sense. But surely, for this to be any use, the JK flip flop must always be in a master slave arrangement else the T flip flop will just be in race around when T is high?

And yet I can't find a single reference confirming that my assumption is true. Am I missing something?

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  • \$\begingroup\$ It is likely that such a thing would be implemented as a state machine (at least that's what I was taught in school). Try searching for "asychronous state machine". \$\endgroup\$ – Austin Nov 6 '15 at 11:20
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A T-FF is IMO always implemented using two level-triggered elements, thus creating an edge-triggered element. In silicon a level-triggered element is easier to implement than a gate-level diagram would suggest, because a transmission gate can be used in the feedback loop.

"T flip flops are just JK flip flops with the same input to J and K" - that is one way to realise a T-FF, but there is no need to start with a JK. A D-FF with /Q fed back to Din is another option.

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  • \$\begingroup\$ Can be comprised of either two or three level-triggered elements. A master-slave FF uses two, but a common edge-triggered D FF design (eg as used in SN74x74) actually uses three S-R latches. However, in modern CMOS, the master-slave design is almost universally used. \$\endgroup\$ – Eric Smith Jul 21 '17 at 6:33

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