In Xilinx ISE, if you check the state-machine examples given in "Language Template" (VHDL->Synthesis Constructs->Coding Examples->State Machines and Verilog->Synthesis Constructs->Coding Examples->State Machines) you'd note that the examples for VHDL are provided in the "two-process" style which separates next state decode (or steering) logic from state storage process (this is the style I practice and I know many professionals strongly encourage this style). However, Verilog examples are just one big "always" block.

I'm just curious why Verilog state-machine templates are provided differently, does anyone have some insight about this difference?


  • 2
    \$\begingroup\$ I use the single process style in VHDL. It's simpler, shorter, easier to get right, and used by most of the professionals I know. But not taught in many textbooks. Some academics seem to have negative opinions of it but I've never seen any substantial reason behind that. \$\endgroup\$
    – user16324
    Nov 6, 2015 at 14:37
  • \$\begingroup\$ @BrianDrummond: thanks for your comment. I wasn't really arguing about which method is best and practical, and I don't have strong objections against it either. I guess everyone should follow the method that works best for them. \$\endgroup\$
    – Ali
    Nov 17, 2015 at 16:11

1 Answer 1


I think it has to do with whoever wrote the example and when the example was originally written. Both single and two always blocks work. For differences in Verilog coding styles, I suggest reading this paper by Cliff Cummings. The paper now a bit dated, but the points are still valid. Experiment with your own synthesizer. I always use the two always blocks (one combinational decoder, one sequential assignment) as recommended in the paper. It gets me the best area, timing, and is ECO friendly with my tool set.

The original IEEE Std 1364-1995, required combinational always blocks to explicitly state every signal in the sensitivity list. If you miss a signal, the synthesizer will still give the correct result, but it may not match the behavior of RTL in simulation. For a state machines machine with many inputs, managing the sensitivity list was tedious. Many designers went with the single always block plus assign statements approach to avoid the risk of making a mistake when managing the sensitivity list. A few used (or wrote there own) scripts the to manage it for them; example the Emacs script Verilog-Mode.

In IEEE Std 1364-2001, the standard introduced @* as an auto sensitivity list. But it took a few years for it to be commonly supported across different simulators, synthesizers and other verilog tools. The examples in your Xilinx ISE was likely written before @* was supported on Xilinx and no one has since did an update overhaul of the examples.


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