1
\$\begingroup\$

I am trying to write a module counter to debounce a input coming from mechanical buttons. The module should be controlled by the 4x4 matrix button module when to start or stop debonce.

This is my counter module

module counter(input clk,input start, input[25:0] stateToGo ,output reg finished);
  reg [25:0]state = 0;
  reg [25:0]nextState = 0;
  //state register
  always@(posedge clk)begin
    state <= nextState;
  end
  //output CL
  always@(posedge clk)begin
    if (start == 1)begin
        if(state == stateToGo)
            finished = 1;
        else 
            finished = 0;
    end
  end
  //next state CL
  always@(posedge clk)begin
    if(start == 1)begin
        if(state == stateToGo)
            nextState = 0;
        else
            nextState = state + 1;
    end
  end
endmodule 

And this other is my keyboardScanner module, but when I connect them witha top module and try to press a button no input is taken from the keyboardScanner:

module keyboardScanner (input wait100,input wait20, input [3:0] col, output reg start,output reg [3:0] row, output reg [7:0] keyCode);
  reg [1:0]state=2'b00;
  reg [1:0]nextState=2'b01;

  //state register
  always@(posedge wait100) begin
    state <= nextState;
  end

  //output CL
  always@(posedge wait100) begin
    case (state)
    2'b00: row <= 4'b0001;
    2'b01: row <= 4'b0010;
    2'b10: row <= 4'b0100;
    2'b11: row <= 4'b1000;
    default: row <= 4'b0001;
    endcase
    if (col != 4'b0000) 
        start = 1;
    if (col != 4'b0000 && wait20 == 1) begin
    keyCode <= {row[1],row[2],row[3],row[0], col[0],col[1],col[2],col[3]};
      start = 0;
    end
  end

  //next state CL
  always @(posedge wait100) begin
    if(wait20 == 0 && start == 1)begin
        case (state)
            2'b00: nextState <= 2'b01;
            2'b01: nextState <= 2'b10;
            2'b10: nextState <= 2'b11;
            2'b11: nextState <= 2'b00;
            default: nextState <= 2'b00;
        endcase
    end
  end

endmodule

Anything going wrong with my counter? If I use CLK and no counter the inputs are taken pretty good from the keyboardScanner FSM

This is my top module with counter:

module comboModule(input clk, input  [3:0]col,output [3:0] row, output CA,CB,CC,CD,CE,CF,CG,AN0,AN1,AN2,AN3,output [7:0]kCode);
     wire finish20,finish100,starter;
     counter c20(clk,starter,26'b00000000011000011010100000, finish20);
     counter c100(clk,1 ,26'b00000001111010000100100000, finish100);
     keyboardScanner kScan(finish100,finish20,col,starter,row,kCode);
     SevenSegment SS(clk, kCode,CA,CB,CC,CD,CE,CF,CG,AN0,AN1,AN2,AN3);
endmodule
\$\endgroup\$
2
\$\begingroup\$

If you're going to insist on using three always blocks for every state machine (excessively pedantic and verbose, in my opinion), you need to do it right: Only the process that updates the state variables should be clocked — the others (marked "next state CL" and "output CL" in comments) should be purely combinatorial; i.e., always @* begin ....

With all three processes clocked in each case, you've got some extra "pipeline" stages going on that are probably messing up your logic.

EDIT:

Although on further perusal, I don't immediately see anything wrong that jumps out at me, assuming that my guesses about how the two modules are wired together are correct. I'd have to see your top-level modules (both versions) to be sure.

When you "use no counter", what are you doing with the wait20 input to the scanner module? If you tie it high, then the next state logic will never run, but if you tie it low, the keyCode output is never set.

\$\endgroup\$
2
  • \$\begingroup\$ I need to do it with 3 always blocks because my instructor wants us to play safe since we all are beginners to this stuff. My code is supposed to read a 4x4 button matrix from a beti board and take a keycode for the pressed button, then display it on a 7-segment display on my basys2 fpga. I am now posting my top module with the clock. \$\endgroup\$
    – anon
    Nov 7 '15 at 13:19
  • \$\begingroup\$ CA,CB... Are cathodes for 7 seg display. And A3 A2... are the anodes. All of those work ok. But when I put the wait100 which is supposed to make my module wait 100ms it doesnt take any input form keyboard anymore, when in input clk in top module in the wait100 input it works but not debouncing \$\endgroup\$
    – anon
    Nov 7 '15 at 13:23

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.