This is a JK Flip-Flop image.

jk flip flop

Using this image is there a way to know if the output changes on raising or falling clock? In other words, is input data transferred to the outputs on the HIGH-to-LOW clock transitions or on the LOW-to-HIGH transition?


The heart of the circuit is the pair of 2-input NAND gates which form a latch. Such a latch is active-low on input. This means that it will be activated when one or both of the 3-input NAND gate outputs goes low. This will happen when all inputs are high.

So the circuit is activated on the rising edge. When it does so, the latch is driven high or low, and the inverted feedback then disables the input.

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  • 2
    \$\begingroup\$ This is not fully correct. This FF is not edge triggered. It's state triggered. As long as CLK is high, J or K can change and cause Q to change. \$\endgroup\$ – Paebbels Nov 7 '15 at 7:36

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