I'm looking to implement a small persistent 'configuration space' parallel EEPROM within a design. However, given the volatile nature of FPGAs, this doesn't seem possible without some very clever manipulation of its attendant flash. I am perhaps mistaken in this assumption (and I would be very grateful for details if that is the case).

That said, the less volatile nature of CPLD configuration intrigues me for this application. I'm looking to implement the top-level design (and subsequent parallel EEPROM) on an XC9500XL variant, and I'm hoping to do this as a single-chip solution (rather than just add an admittedly cheap external parallel EEPROM).

Thoughts? Advice? "JFGI"-death-threats? Any help is appreciated!

  • \$\begingroup\$ Have you considered a Flash-based FPGA such as one of the Microsemi (ex-Actel) or Lattice parts? \$\endgroup\$ – ThreePhaseEel Nov 7 '15 at 2:47
  • \$\begingroup\$ I've actually been meaning to play around with Lattice components, and this may be a perfect excuse. However, I'm still lost on how I would invoke such functionality. Would a standard array ROM just inherently have persistence due to the physical configuration structure? \$\endgroup\$ – Chris Nov 7 '15 at 3:09
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    \$\begingroup\$ Why does just using an external EEPROM not solve your problem? What is the actual problem you are trying to solve? \$\endgroup\$ – The Photon Nov 7 '15 at 3:20
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    \$\begingroup\$ BTW, don't mess around with some old CPLD like XC9500XL. Have a look at newer CPLDs from Altera or Lattice...they are essentially small FPGAs with integrated non-volatile storage. Depending on the scale of logic you need, they could be a solution to your problem. \$\endgroup\$ – The Photon Nov 7 '15 at 3:23
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    \$\begingroup\$ I have a simple controller that I can squeeze onto the aforementioned CPLD, but I'd like to make some settings alterable with persistence - by way of storing parameters in an externally accessible internal EEPROM (to avoid reconfiguring the entire chip). The desire to incorporate this persistent storage onto the CPLD is purely from a desire to have a single-chip solution. Mostly an 'if it can be done, I'd like to do it' approach. Should it prove unviable, or far more trouble than it's worth, I will likely just incorporate an external EEPROM into the overall design. \$\endgroup\$ – Chris Nov 7 '15 at 3:43

You can't create EEPROM/FLASH out of generic device resources. Any solution will be inherently device family specific

Many CPLDs and FPGAs with internal non-volatile memory will have some spare and a method of accessing that memory. This is certainly true of the Altera MAX V and MAX 10. The block natively presents itself with an Altera-specific serial interface but Altera provides an IP block that wraps this to provide various types of serial and parallel interfaces.

The MAX V chips have 8 kilobits of user flash memory which doesn't sound like much by today's standards but should be enough for basic configuration, the MAX 10 chips have a lot more.

Similarly FPGAs that boot from with external flash memory often provide a way for you to talk to the memory chip after the FPGA has booted allowing you to read and write user data from spare areas in that memory.

  1. Modern Xilinx FPGAs have features like:

    • eFuse
    • USER register

    maybe this covers already your needs.

  2. The provided flash memory is mostly designed to store atleast 2 designs. This flash can be read and write from the FPGA. So you could use a memory space at the end.

  3. Most boards are equipped with serial devices like:

    • OneWire EEPROMs
    • IIC RealTime clocks with embedded non-volatile memory (battery backupped)
    • SPI serial flash memory chips
    • ...
  4. It's even possible to look into the network PHY for some nvram / EEPROM :)


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