I'm looking to implement a small persistent 'configuration space' parallel EEPROM within a design. However, given the volatile nature of FPGAs, this doesn't seem possible without some very clever manipulation of its attendant flash. I am perhaps mistaken in this assumption (and I would be very grateful for details if that is the case).
That said, the less volatile nature of CPLD configuration intrigues me for this application. I'm looking to implement the top-level design (and subsequent parallel EEPROM) on an XC9500XL variant, and I'm hoping to do this as a single-chip solution (rather than just add an admittedly cheap external parallel EEPROM).
Thoughts? Advice? "JFGI"-death-threats? Any help is appreciated!