# System Verilog generic modules and unused ports

I have written a parametrized FIFO for reuse. Since I want to use the FIFO in multiple places I added several output signals for the fill state, like full, empty, almostFull and almostEmpty.

However sometimes not all of the output signals are used, resulting in warnings about unused signals and that the associated logic will be removed. These warnings clutter the message pane.

## Question

What is the correct way to design a generic module like a FIFO, and avoid warnings about unused ports (while using interfaces for the connection)?

Related questions:

I do not think https://stackoverflow.com/a/22272949/258418 is the way to go, since I am happy for the synthesis tool to rip it out, I simply don't want a warning for dead code removal.

While How to remove this warning in Verilog? looks related, it does not help, since I can't just remove the offending logic/wires, since they might be used by other instances of the code.

There is nothing in the SystemVerilog language that allows you to specify outputs that are allowed to be left unconnected. And you don't want to globally turn off dead code removal warnings because that could mask much larger problems. I see three possible choices:

1. Write a script that filters your messages to eliminate the warnings from the dead logic that is OK to remove.
2. Create separate versions of your FIFO with different sets of outputs and instantiate the correct version depending on which version is needed. I realize this goes against the generic solution you are looking for, but the use of macros or submodules might make it a little more reusable.
3. Live with it the way the messages are now.
• Solution two seems to be the cleanest. However, having 2^optionalOutputs different implementations seems rather cumbersome, if I can not write it as one parametrized module.
– ted
Nov 8 '15 at 10:17
• I was dreading this answer (and keep hoping for another day that there is a better way, before accepting). This seems to be a very reasonable desire, yet to be imossible :/
– ted
Nov 8 '15 at 10:18
• i would go with option 1. the synthesizer you use will in any case complain about unused pins and their associated logic. in your synthesis script, add a few lines that take care of the warnings, and ship that script with the generic code. i think this would be guarantee the easiest reuse of the code. Dec 11 '15 at 2:14

What you want can be achieved by using SystemVerilog interfaces and modports. You can create an interface that has all the FIFO related signals. Then you define modports for different usages where each modport exposes only a subset of your interface signals.

This way you can keep only one FIFO description file, which can also include the interface and its modport description.

See Chapter 25.5 of SystemVerilog LRM IEEE Std 1800-2012.