I have written a parametrized FIFO for reuse. Since I want to use the FIFO in multiple places I added several output signals for the fill state, like
However sometimes not all of the output signals are used, resulting in warnings about unused signals and that the associated logic will be removed. These warnings clutter the message pane.
What is the correct way to design a generic module like a FIFO, and avoid warnings about unused ports (while using interfaces for the connection)?
I do not think https://stackoverflow.com/a/22272949/258418 is the way to go, since I am happy for the synthesis tool to rip it out, I simply don't want a warning for dead code removal.
While How to remove this warning in Verilog? looks related, it does not help, since I can't just remove the offending logic/wires, since they might be used by other instances of the code.