# How this for loop could be translated efficiently in vhdl using for generate statements?

Hi guys i have this pseudo-code nested for loop (very simple to translate in C)

Input : x; //is an unsigned
Output : y;

val = 0;
for i = 0:n-1
for j = 0:n-1
if( ((x >> i) & 0x1) && ((x >> j) & 0x1) )
val = val + x << (i + j);

y = val;


Is there a way to translate this using for-generate statments in VHDL? I'm aware of the fact that i could implement basically the same code using process and sequential for loop, but it is possible to do something similar using the for generate instead?

(my main issue is that there's no variable in concurrent statements).

The obvious way to do it using if ... generate would be to make Val a 2-D array signal, which makes the "unrolling" into parallel hardware absolutely explicit. (or an n * n sized 1-D array) But that is more complex and error-prone than the simple process approach.
• Yes I am suggesting the process is simpler and better. If I got stuck debugging, I would consider ALSO adding an array of signals and assigning debug(j) <= val; inside the inner loop. Either delete it when done, or hide it from synthesis with --pragma translate off or your tool's equivalent so that only simulation sees it. – Brian Drummond Nov 10 '15 at 14:10