Hi guys i have this pseudo-code nested for loop (very simple to translate in C)

Input : x; //is an unsigned
Output : y;

val = 0;
for i = 0:n-1
  for j = 0:n-1
    if( ((x >> i) & 0x1) && ((x >> j) & 0x1) )
        val = val + x << (i + j);

y = val;

Is there a way to translate this using for-generate statments in VHDL? I'm aware of the fact that i could implement basically the same code using process and sequential for loop, but it is possible to do something similar using the for generate instead?

(my main issue is that there's no variable in concurrent statements).


1 Answer 1


If you use for loops within a process, you can use a variable. This (translated into valid VHDL) should synthesise fine (assuming n is a constant or generic).

The resulting hardware may be large or slow, but the same would be true if you used generate statements. If it doesn't meet your size or speed goals, you get to play with clocked processes, and pipelining.

The obvious way to do it using if ... generate would be to make Val a 2-D array signal, which makes the "unrolling" into parallel hardware absolutely explicit. (or an n * n sized 1-D array) But that is more complex and error-prone than the simple process approach.

  • \$\begingroup\$ As far as i know, but i could be wrong, is that debugging signals is easier than debugging variable, this is why i'm asking for concurrent statement. \$\endgroup\$ Commented Nov 10, 2015 at 13:31
  • \$\begingroup\$ Anyway in summary you suggest that a simple process with a nested for cycle and a simple statement <code>val := val +...</code> is it better? \$\endgroup\$ Commented Nov 10, 2015 at 13:42
  • \$\begingroup\$ Yes I am suggesting the process is simpler and better. If I got stuck debugging, I would consider ALSO adding an array of signals and assigning debug(j) <= val; inside the inner loop. Either delete it when done, or hide it from synthesis with --pragma translate off or your tool's equivalent so that only simulation sees it. \$\endgroup\$
    – user16324
    Commented Nov 10, 2015 at 14:10
  • \$\begingroup\$ Ok, let's try with that... \$\endgroup\$ Commented Nov 10, 2015 at 14:21

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