Hi guys i have this pseudo-code nested for loop (very simple to translate in C) Input : x; //is an unsigned Output : y; val = 0; for i = 0:n-1 for j = 0:n-1 if( ((x >> i) & 0x1) && ((x >> j) & 0x1) ) val = val + x << (i + j); y = val;
Is there a way to translate this using
for-generate statments in VHDL? I'm aware of the fact that i could implement basically the same code using process and sequential for loop, but it is possible to do something similar using the for generate instead?
(my main issue is that there's no variable in concurrent statements).