cventu has provided a good answer as to why two capacitors might be needed between Vb and Vs of the IR2104. Sometimes, when \$f_{\text{pwm}}\$ is a very low frequency like 60Hz or so, a large amount of capacitance is required to support the current demands of the high side drive.
But in truth, we have no idea why the OP of the linked question used such a large amount of capacitance since there is no mention of the value of \$f_{\text{pwm}}\$. That's too bad too, because knowing \$f_{\text{pwm}}\$ is key to knowing how much bootstrap capacitance to use. Usually for higher values of \$f_{\text{pwm}}\$ (like ~100kHz) a bootstrap capacitance of only a few tenths of a \$\mu F\$ are needed.
To determine how much bootstrap capacitance to use, it is necessary to know \$f_{\text{pwm}}\$, \$Q_g\$ (FET gate charge), \$I_{\text{bs}}\$ (bias current IR2104 high side), and \$\Delta V_{\text{bs}}\$ (change of IR2104 high side bias voltage). Then use the voltage-current relation of a capacitor:
\$i(t)\$ = \$C\frac{ \text{ dV}}{\text{dt}}\$
to calculate \$C_{\text{bs}}\$. Let's pretend that \$i(t)\$ is a constant so:
\$C\$ = \$\frac{I\Delta T}{\Delta V}\$; where \$I\$ = \$Q_g f_{\text{pwm}} + I_{\text{bs}}\$ and \$\Delta T\$=\$\frac{1}{f_{\text{pwm}}}\$
\$C_{\text{bs}}\$ ~ \$\frac{Q_g f_{\text{pwm}} + I_{\text{bs}}}{f_{\text{pwm}}\Delta V}\$
Let's say that \$Q_g\$ = 30nC (about like an IRF530), \$I_{\text{bs}}\$ = 50\$\mu A\$ (about like IR2104), \$f_{\text{pwm}}\$ = 100kHz, and \$\Delta V_{\text{bs}}\$ = 0.1V. Then:
\$C_{\text{bs}}\$ ~ \$\frac{(30nC)( 100{\text{kHz}}) +50\mu A}{(100{\text{kHz}})(0.1V)}\$ ~ \$0.33\mu F\$
So, for \$f_{\text{pwm}}\$ in the tens of kHz, \$C_{\text{bs}}\$ only needs to be a single ceramic part.
The IR2104 is pretty easy to use since you only have to provide \$V_{\text{cc}}\$ > 10V, and drive one input (IN) with PWM signal. Generation of high side and low side output timing is taken care of for you. When IN is low, \$V_{\text{LO}}\$ will be high, turning on the low side FET and charging \$C_{\text{bs}}\$ while \$V_{\text{HO}}\$ is low and high side FET is off. When IN is high, \$V_{\text{LO}}\$ will be low, turning off the low side FET, while \$V_{\text{HO}}\$ is high and high side FET is turned on removing some charge from \$C_{\text{bs}}\$ resulting in \$\Delta V_{\text{bs}}\$.
