# How do digital watches use so little power (and how do I do that?) [duplicate]

The title of the question is pretty self-explanatory.

I did a quick back-of-the-envelope calculation for my own digital calculator watch (the Casio CA-53W for those who are interested). The battery is supposed to last around 5 years on the 90 mAh coin cell inside. This means that the watch must be using $$0.090\ \mathrm{Ah}\ /\ (5\ \mathrm{years} * 365\mathrm{\frac{days}{year}} * 24\mathrm{\frac{hours}{day}}) = 2.055\times10^{-6}$$ or just over 2 µA!!!

Now, I know that with enough tweaking, the ubiquitous ATMega328p can use as little as 1 µA, and there are specialized microcontrollers out there that use even less, say in the tens of nanoamps...

...but what about the display? My watch shows the time on a 7-segment lcd, and the display is never off. Where on Earth can I find a display that only uses something on the order of 1 or 2 µA??

(Incidentally, I'm just trying to make own simple Reverse Polish calculator watch, kind of like the µwatch project at calcwatch.com, but with a focus on long battery life.)

Would I need to buy an fpga, fuse my own logic circuit onto it, and somehow hack the display out of an old watch to get these kinds of results? Is there an easier way?

• It's because the watch only updates once a second, which is glacial for a microcontroller, and the displays used really don't take much current at all. – Passerby Nov 11 '15 at 4:18
• The digital watch uses a 32kHz crystal to run a counter. And that is about it. There is no processor. LCD display requires very little power. – mkeith Nov 11 '15 at 4:19
• the LCD still needs refreshes several times a second – Jasen Nov 11 '15 at 4:54
• I'm more or less aware of tricks for using less power on a microcontroller, but where do I get my hands on these glass lcd displays? – Mahkoe Nov 11 '15 at 5:01
• The chip that drives the watch will be built specifically to run very slowly with very low quiescent current. Many microcontrollers will have far too much leakage current. FPGAs are completely out of the question, they can draw many mA of leakage current even before they are configured. There are all sorts of tricks that you can play as a circuit designer to get very low leakage (though rather slow) circuits. One technique is subthreshold logic where the transistors never fully turn on. It is possible for chips built in this way to use less than 1% of the power of a traditional chip. – alex.forencich Nov 11 '15 at 5:16