I'm using 0.01 uF decoupling capacitors in a 0805 package, on each Vcc/GND pair of my CPLDs. So, around eight capacitors in total). I find it a bit easier to route the board if the decoupling capacitors are placed on the bottom layer and connected to the Vcc and GND pins of the CPLD/MCU using vias.

Is this a good practice? I understand the aim is to minimize the current loop between the chip and the capacitor.

My bottom layer also serves as a ground plane. (it's a two-layer board, so I don't have a Vcc plane), and so I don't need to connect the ground pin of the capacitor using vias. Obviously, the chip's GND pin is connected using a via. Here's a picture that illustrates this better:

enter image description here

The thick trace coming toward the capacitor is Vcc (3.3 V) and it's connected to another thick trace that comes straight from the power source. I provide Vcc to all the capacitors in this way. Is it a good practice to connect all the decoupling capacitors in such a way or will I run into problems down the road?

An alternative way that I've seen being used is that there is a single trace for Vcc and another for GND that runs from the power source. The decoupling capacitors then 'tap' into those traces. I noticed that in that approach there was no ground plane - just thick Vcc and GND traces running from a single point. A bit like my Vcc approach described in the previous paragraph, but also adopted for GND.

Which approach would be better?

enter image description here

Figure 2

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Figure 3

Here are some more pictures of the decoupling capacitors. I think out of these the best is the one where the capacitor is at the top layer - do you guys agree?

I'll obviously need one via for the GND pin if I want it to connect to the ground plane. Regarding the value, 0.001 uF to 0.1 uF was specified in Altera's documentation and so I settled at 0.01 uF. Unfortunately, even though I mentally noted that I'll need another capacitor at less 3 cm, I didn't remember to implement it on the schematic. Based on the suggestions here, I'll also add 1 uF capacitor in parallel to each Vdd/GND pair.

Regarding power - I'll be using 100 logic elements for a 100-bit shift register. The frequency of operation is largely dependent on the SPI interface of the MCU that I'll use to read the shift register. I'll be using the slowest frequency that the AVR Mega 128L allows for SPI (i.e. 62.5 kHz). The microcontroller will be at 8 MHz using its internal oscillator.

Reading the answers below, I'm now quite concerned about my ground plane. If I understand Olin's answer, I should not connect the GND pin of each capacitor to the ground plane. Instead, I should connect the GND pins to the main GND net on the top layer and then connect that GND network to the main return. Am I correct here?

If this is the case, should I have a ground plane at all? The only other chips on the board are an MCU and another CLPD (same device, though). Other than that, it's just a bunch of headers, connectors and passive elements.

Here's the CPLD with 1 uF capacitors and a star-network for Vcc. Does this look like a better design?

enter image description here

My worry now is that the star point (or area) will interfere with the ground plane, as they're on the same layer. Also note, I'm connecting Vcc to just the larger capacitors' Vcc pin. Is this good or should I connect Vcc to each capacitor individually?

Oh and please don't mind the illogical capacitor labeling. I'm going to fix it now.

  • 1
    \$\begingroup\$ 0805 is really quite a large package to be using for a 10nF decoupling cap. The package inductance is going to be significant resulting in poor de-coupling at higher frequencies which is what the cap is there for. Adding in the inductance of the via only makes this issue worse. You may even find that between the inductance of an 0805 package and the via that you've completely negated the benefit of the cap in the first. Thus the first thing I would do is consider a package change, 0402 preferably 0603 max. \$\endgroup\$
    – Mark
    Commented Sep 26, 2011 at 12:56

6 Answers 6


At least for this capacitor you seem to be able to place it on the top layer. If you would place it there at the same coordinates you would shorten the distance between cap and IC pins by at least 80% (you also have to calculate the PCB's thickness). I would definitely try to do so. You can even move it a bit closer. Don't listen to Russell :-) when he says that it doesn't make a difference if you need the via anyway; it's the distance between cap and the \$V_{DD}/V_{SS}\$ pins that counts.
Also, depending on the CPLD's power needs the 10nF may be a little bit small, though this might be more of a problem for FPGAs than CPLDs. Depends both on the number of gates and the clock frequency. Still, when I use a 10nF cap I place a 1\$\mu\$F cap in parallel, with the 10nF the closest to the pins.
Daisy chaining your loads on a single power trace is not a good idea. Instead make the power supply's output a star point and connect your different devices on different traces, each with their own decoupling.

Your third screenshot is definitely the best, decoupling-wise. (I would even let the traces go straight down.) I see no problem with the ground plane, nor with vias connecting to it. Just don't place the via between the cap and the CPLD pins. Distance caps-CPLD should be very short, if possible even shorter! :-)

edit 2
I didn't pay attention to the package first, but your fourth screenshot makes it obvious: your caps' packages are huge. I see Mark made a note about it as well, and I agree with him: switch to a smaller size. 0402 is pretty standard these days, and your PCB assembly shop may do 0201s as well. (AVX has 10nF X7R in 0201 package.) A smaller package will allow you to place the capacitor closer to the IC, yet still leave room for neighboring traces.

Further reading
Choosing MLC Capacitors For Bypass/Decoupling Applications. AVX document
Using Decoupling Capacitors. Cypress document

  • \$\begingroup\$ Thanks Steven! Reading the links now. I've updated the question regarding the power and frequency requirements. \$\endgroup\$
    – Saad
    Commented Sep 26, 2011 at 13:39
  • \$\begingroup\$ @Saad - Your number of gates is rather low, and so is your frequency, so 10nF might be OK. I would still place 1\$\mu\$F parallel for each couple of decoupling caps. Add an extra one if the distance becomes too large (a few cm). \$\endgroup\$
    – stevenvh
    Commented Sep 26, 2011 at 14:00
  • \$\begingroup\$ Yes. I should add this is only per each CPLD. The end goal is to combine 3 CPLDs and make a 300-bit shift register - I understand I could get a large CPLD, but I can't utilize the shift register then as we can only handle TQFP packages (no BGA!). However, the above design is for a prototype only and I'm keeping things simple. But I think the final board will not have 3 CPLDs per PCB. Instead, the design will be modular. But I'll ask advice regarding that when I'm ready to route those boards. I need to get the prototype running first. But are you sure 1uF is ok? The doc. suggests 47uF to 100uF. \$\endgroup\$
    – Saad
    Commented Sep 26, 2011 at 14:07
  • \$\begingroup\$ The problem with smaller packages is this is a prototype and as such, I intend to solder it by hand(!) - would you still recommend so? I could always switch to 0603 for production. Also, as far as I know, the local machinery here does not do any package below 0603, so thats an issue in itself. I will inquire further, however. Do you think the power distribution is better now? \$\endgroup\$
    – Saad
    Commented Sep 26, 2011 at 15:29
  • \$\begingroup\$ @Saad - Yes it looks better. Maybe wider traces, you're already cutting through your ground plane anyway. I'm using Erem 102ACA tweezers, which are good for up to 0402s. I've never tried 0201s, but I can imagine they're hard to solder with an iron. A reflow oven should work, though. \$\endgroup\$
    – stevenvh
    Commented Sep 26, 2011 at 15:58

I agree that in general its not a big deal if bypass caps are put on the other side of the board from the chip they are bypassing. With BGA packages, this is the only way to bypass some power/ground pairs. The point is to minimize the bypass cap loop. If the best way to achieve that is to put the bypass cap under the chip, then that's OK.

However, in your case it makes no sense. You have nothing on the top layer where the cap would be, so connect it directly to the pins and add one via to the ground layer.

There is another reason I don't like your layout independent of bypassing. You are running the connection between the chip ground pin and the ground side of the bypass cap accross the main ground plane. Now you have a center-fed patch antenna instead of a ground plane. Try to keep the high frequency loop currents off the ground plane. Make sure the loop between chip and bypass cap is as short as you can reasonably make it, then connect the ground part of that loop to the master ground net in one place. The same goes for the power part of the loop. That keeps the high frequency currents contained while still providing good ground and power connections. This doesn't matter to bypassing, but it does matter in regards to RF emissions.


The aim (as you know) is to provide as low an impedance as possible between power and ground, so keeping the traces (from pin to capacitor) as short as possible is important. A 4 or more layer board is a lot easier to achieve good high frequency performance with, but with care it can be done on a 2-layer board.

I have made quite a few 2-layer FPGA test boards and use the method Steven mentions with cap and traces on the same layer - usually I would use a 100nF and 10nF right next to each other on each set of power pins (the 10nF closest to the pins) with a couple of 1uF and 10uF further out.

If you use vias in the above design, then ideally the first thing the traces meet is the capacitor, not the vias (i.e like mentioned above, but with vias) So in your above design, if you have the capacitor pads in between pins and vias, and right next to the vias (i.e. no trace, like via is extension of pad) then you create as small a loop as possible. If you have the cap on the underside (very common to have them "underneath" the IC with vias to ground/power plane) then just keep a very short path to via from pin, then the cap right next to the via on the other side.

Keeping impedance down over a wide bandwidth is important. Capacitors of different values have different SRF (self resonant frequencies) usually the larger the cap the lower the SRF. So placing e.g. 2 x 1uF, 4 x 100nF, 8 x 10nF on your CPLD/FPGA rails will help to provide this. If you look at the vendor app notes, or a dev board schematic you should see a decoupling system quite similar to that described above.

Here is an example of capacitor impedance over frequency (from a TI document):

Cap impedance

  • 1
    \$\begingroup\$ Altera's Power Distribution Network app notes go into a lot more detail, like how to determine the needed power network impedance (the actual impedance needs to stay below this) and the maximum frequency (beyond which the PCB impedance doesn't matter as much as on-chip inductance). Also, this graph leaves out the power supply, which keeps impedance low for lower frequencies (1-100 kHz) by means of its negative feedback control loop. \$\endgroup\$ Commented Sep 26, 2011 at 14:07

Cap on top or bottom makes no real difference if you must use a via both ways.

In this case cap on bottom is good as you get direct earth connection and use of a via or equivalent is unavoidable.

BUT you say you understand that the aim is to minimise the loop between chip and cap - and then you make an unnecessary one. It's not vastly large but its much larger than it needs to be. You run from the cap, under the IC pads to the via and then back to the IC pads again. You could either put the via on the outside of the IC next to the cap so yoi'd have about zero loop between cap and IC or, possibly better, put the cap UNDER the IC either just below the vias as shown here or, electrically best of all, n=move the vias down somewhat and place the cap right against the vias where the tracks to the IC meet the vias for minimum possible loop.

Does it matter? - quite possibly not. But if you can get the cap right against the IC pins at about zero cost its good to do so.

There is a potentially more serious issue:

You ask about VCC/Gnd distribution using track/track or track groundplane.
Of these track/groundplane is potentially better as it can help minimise ground impedance BUT the "slots" that the tracks on the bottom cut through the groundplane "landscape" can cause much trouble. As shown there you have a nice little radiating antenna in a slot in the bottom layer. it runs from IC+ via left hand via then in slot to the cap +ve. That is probably a useful coupling loop at a few hundred MHz.

Elsewhere you may take +ve in a top track across a ground plane slot and then connect to a remote point (say an IC +ve,) and connect the IC ground pin to the ground plane at the IC. Current will then flow via top track, over slot, into IC, out if IC gnd pin, into groundplane, via gp towards power supply but meeting the slot on the way. To get around the slot it will travel sideways to a suitably low impedance path around the slot, then back to under the top track and on its way. The ground current flow along the sides of and around the slot make a very nice UHF transmitter. And also may act as a receiver.

Some people have to design these in - you can have them for free :-(.

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Freescale application note - Compact Integrated Antennas says:

enter image description here

Worst case you may be better off with two top tracks for ground and V+ if you can balance the path to each and minimise the intertrack separation at all points. Star distribution is best if practicable. Where you cannot avoid having several feeds on one power supply track ensure that the signals placed on the track pair by components in one location do not adversely affect others on the same track pair. void at all costs having multiple track based power supply paths to a single powered location. In the classic ideal and seldom fully realisable system all power feeds are in star arrangement joining only at the power supply.

  • \$\begingroup\$ Russel, thanks for the insight. I'm having a hard time understanding Slot Antennas, though. So I apologize for asking again: is it bad to have tracks running through the ground plane? Does the ground plane need to completely unbroken? I only have two layers and quite a few IO lines that I need to route and while I try to keep everything on the top layer, sometimes its necessary to go on the bottom layer. So, my question is, is it better to have a broken ground plane then no ground plane at all? \$\endgroup\$
    – Saad
    Commented Sep 26, 2011 at 13:38
  • \$\begingroup\$ The problem occurs when the "go" circuit crosses a break in the ground plane but the return current needs to take a detour around the break. You get an effective current loop and this can be very significant. The return current needs to b able to mirror the send current so the overall loop area is minimised. \$\endgroup\$
    – Russell McMahon
    Commented Sep 26, 2011 at 16:48

If you put the caps on the bottom, then the board will need an addition run through the pick 'n place and reflow oven. This will add cost to the finished board.


Somewhat off topic, but since your frequency requirements are (very) modest, you have the option of lowering the drive strength or slew rate on your CPLD (if supported). The steeper the logic transition, the more high-frequency components contained. A slower slew rate will reduce switching transients and reduce demands on your decoupling network.


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