0
\$\begingroup\$

I know that RAM is a word used to describe a type of memory that is volatile and more importantly doesn't have a speed difference when accessing different parts of the "memory grid". Isn't the last characteristic of RAM(no speed difference between accessing different areas of the memory) technically not possible because it depends on the length of the wires going to that intersection of the grid from the two decoders?I know that some of my terms are incorrect and may be misleading so here is an example diagram of a RAM chip(on the first page there is an architectural diagram):

http://users.ece.utexas.edu/~valvano/Datasheets/6264.pdf

On the datasheet the "memory grid" is called the array, and two decoders are used with the address input so that one "intersection" can only be "active" at once.

\$\endgroup\$

closed as primarily opinion-based by pjc50, jippie, Daniel Grillo, PeterJ, W5VO Nov 15 '15 at 18:25

Many good questions generate some degree of opinion based on expert experience, but answers to this question will tend to be almost entirely based on opinions, rather than facts, references, or specific expertise. If this question can be reworded to fit the rules in the help center, please edit the question.

  • 1
    \$\begingroup\$ where does the word RAM describe anything about the speed? \$\endgroup\$ – PlasmaHH Nov 11 '15 at 15:39
  • \$\begingroup\$ RAM stands for Random Access Memory which basically means that any random part of RAM can be "chosen" and accessed without any speed difference compared to accessing a different random part of RAM. Correct me if I am wrong. \$\endgroup\$ – zack1544 Nov 11 '15 at 15:42
  • 6
    \$\begingroup\$ (a) this is useless pedantry of the worst kind (b) at that length the wire behaves more like a lumped capacitance (c) the read delay in the chip is fixed at worst-case as there's no way of measuring when the signal has arrived \$\endgroup\$ – pjc50 Nov 11 '15 at 15:44
  • 4
    \$\begingroup\$ RAM has nothing to do with volatility. FeRAM, PCRAM (PRAM), Battery Backed SRAM, etc. are all non-volatile. \$\endgroup\$ – Tom Carpenter Nov 11 '15 at 16:02
  • 1
    \$\begingroup\$ Wait, do you mean my "fixed" or "hard" disk is sometimes neither, as well?! Is everything I've ever heard a lie? \$\endgroup\$ – user65586 Nov 11 '15 at 17:37
8
\$\begingroup\$

Isn't the last characteristic of RAM(no speed difference between accessing different areas of the memory) technically not possible

Wikipedia says "almost same amount of time irrespective of the physical location of data inside the memory". And then

Even within a hierarchy level such as DRAM, the specific row, column, bank, rank, channel, or interleave organization of the components make the access time variable, although not to the extent that rotating storage media or a tape is variable.

And to stick with DRAM as example

DRAM bank latency

  • Simple CAS if row is “open” OR
  • RAS + CAS if array precharged OR
  • PRE + RAS + CAS (worst case)

The speed differences are going to be less significant in a SRAM, which lacks this more complicated access model that DRAM has.

Here's a latency (=speed) comparison in an actual (albeit fairly old) system:

enter image description here

There's almost no discernible latency (=speed) variation for SRAM, but there's a lot more for DRAM. The sudden vertical you see is when the SRAM (bandwidth) saturates.

And you do have intra-die latency variations between cells even for SRAM; the following graph is for a [simulated] 45nm process. SECDEC ECC can be used to mask away the speed of the slowest cells; otherwise these would determine the (speed/latency) performance of the entire chip as the lowest common denominator.

enter image description here

And, yeah, even from a purely geometric/layout perspective, ignoring process variations, you'd have some speed difference between SRAM cells. That thesis says that in simulation [of 64Kb SRAM in 65nm process] the speed difference between the slowest (farthest) and fastest (closest) cell is between 5% and 15% based on layout alone.

enter image description here

Not that any of this is reason not to call it RAM anymore.

\$\endgroup\$
8
\$\begingroup\$

The term RAM comes from the historic division between sequentially accessed memory (mercury delay lines, rotating drums and the like) and random accessible memory (like wilkinson tubes and ferrite core memory). All these memories were read-write (but in most cases a read was destructive or even time-boxed), so there was no urge to make a distinction between read-write and read-only. Of these types of memory only RAM survived, so we are stuck with that term for memory that can be read and written, and can be addressed (almost) at will, without (much) speed impact.

Some time later, memories began to appear that could be read, but not written (IIRC the bits were 'wired' by winding a wire clockwise or anti-clockwise around a peg). Those memories were randomly accessible, but to distinguish them from the read-write memory they were called Read-Only Memory or ROM.

Now we have all types of memory that are fussing the borders, like flash, which is a mostly-read but you-can-write-it-some-number-of-times memory.

So yes, the term RAM is at least partially misleading, but we are stuck with it.

(For you to research: why is a file that contains the image of a crashed program often called a 'core dump'?)

\$\endgroup\$
3
\$\begingroup\$

"I know that RAM is a word used to describe a type of memory that is volatile and more importantly doesn't have a speed difference when accessing different parts of the "memory grid".

Well, no. RAM (random access memory) refers only to the ability of the system to modify the contents of the memory, as opposed to ROM (read-only memory) which cannot ordinarily be modified by the system. The distinction between the two has blurred considerably in recent years, both in terms of self-modification and volatility. Flash memory, for instance, for BIOS storage is ordinarily treated as a ROM, but it can be modified. Likewise, even 25 years ago Dallas Semiconductors was selling non-volatile RAMs, which had a backup battery as part of the package. So your ideas about RAM are clearly wrong.

If you could provide a source for your claim about speed differences, it would be helpful.

In modern systems, RAM timing is fixed, but this has not always been so. For example, in the old PC expansion scheme (ISA bus) any memory accessed by the system had the possibility of wait states being asserted by the accessed memory, and each physically distinct memory could assert a different number of wait states. The same was true of most minicomputer architectures. As a result, it was perfectly possible to mix memory cards, with wildly different access times available to the processor.

\$\endgroup\$
  • \$\begingroup\$ I have always interpreted the intended meaning of "RAM timing" to be within a single chip, or bank of chips with common timing and control, and not across an expansion bus. Expansion buses are usually intended to support a range of technology, beyond RAM. In that case, the last para feels a bit misleading if the OP is focused on RAM timing. Also the fact that different blocks of RAM have different timing is not necessarily in conflict with one interpretation of the OP's question, and may even be saying that their proposition (longer wires) is correct (which I don't think is). \$\endgroup\$ – gbulmer Nov 11 '15 at 16:42
  • \$\begingroup\$ @gbulmer - Nowadays RAM timing is generally used wrt a single chip or module, as you say. This is a consequence of current PC design, which uses a minimum number of physical components for RAM functions. It in no way applies to other, older technologies, many of which are still lurking around in legacy systems. \$\endgroup\$ – WhatRoughBeast Nov 11 '15 at 16:53
  • \$\begingroup\$ I still have (somewhere in the house) my old 80286 with 2MB expansion board. I worked on PDP11-34 with memory cards. I had an intimate working knowledge of them. However, my interpretation of the core of the OP's question "(no speed difference between accessing different areas of the memory) technically not possible because it depends on the length of the wires going to that intersection of the grid from the two decoders" is only and exactly talking about the internals of a single chip. \$\endgroup\$ – gbulmer Nov 11 '15 at 16:59
  • \$\begingroup\$ AMD used to make a static RAM which had an internal mechanism to provide a "data ready" output valid for each address. This would allow running any array of chips at maximum speed. \$\endgroup\$ – WhatRoughBeast Nov 11 '15 at 17:07
  • \$\begingroup\$ IIRC lots of manufacturers made chips that way with variations on read and write, like 'Data Valid', 'Data Latched'. So are you saying that the manufacturers asserted that signal more rapidly when the data within the chip travelled over shorter wires (and hence is relevant to the OPs question)? I don't think they did that. I think it was to support CPU to RAM protocols. \$\endgroup\$ – gbulmer Nov 11 '15 at 17:12

Not the answer you're looking for? Browse other questions tagged or ask your own question.