Isn't the last characteristic of RAM(no speed difference between accessing different areas of the memory) technically not possible
Wikipedia says "almost same amount of time irrespective of the physical location of data inside the memory". And then
Even within a hierarchy level such as DRAM, the specific row, column, bank, rank, channel, or interleave organization of the components make the access time variable, although not to the extent that rotating storage media or a tape is variable.
And to stick with DRAM as example
DRAM bank latency
- Simple CAS if row is “open” OR
- RAS + CAS if array precharged OR
- PRE + RAS + CAS (worst case)
The speed differences are going to be less significant in a SRAM, which lacks this more complicated access model that DRAM has.
Here's a latency (=speed) comparison in an actual (albeit fairly old) system:
There's almost no discernible latency (=speed) variation for SRAM, but there's a lot more for DRAM. The sudden vertical you see is when the SRAM (bandwidth) saturates.
And you do have intra-die latency variations between cells even for SRAM; the following graph is for a [simulated] 45nm process. SECDEC ECC can be used to mask away the speed of the slowest cells; otherwise these would determine the (speed/latency) performance of the entire chip as the lowest common denominator.
And, yeah, even from a purely geometric/layout perspective, ignoring process variations, you'd have some speed difference between SRAM cells. That thesis says that in simulation [of 64Kb SRAM in 65nm process] the speed difference between the slowest (farthest) and fastest (closest) cell is between 5% and 15% based on layout alone.
Not that any of this is reason not to call it RAM anymore.