I've implemented a circuit under a suggestion which solves stability issues when driving a MOSFET with an high capacitance, using an OpAmp. Now, the circuit suggested is this one, in which is modeled the MOS and AC1 is used to model the error in the loop (which can be another question, since I'm not so familiar with these models):
The introduction of C1 instead of open circuit and R1 instead of short circuit, will reduces the bandwidth down to the R1*C1 pole, annihilating high frequency oscillations and increasing the margin phase. Mathematically/electrically speaking, I can't see this pole in the output current flowing in Rs, so I don't understand how it can reduces the bandwidth. In the practice, this circuit works very well: it actually annihilates any oscillation.
I can't understand how.