0
\$\begingroup\$

According to what i have read from book Bootstrapping occurs because of capacitance b/w Gate & drain of mosfet,Bootstrapping Phenomenon results into Glitches at the output.I have read from somewhere that Bootstrapping Phenomenon occurs due to high frequency of input voltage.

Here is the image of extract on Bootstrapping from book CMOS VLSI Design by weste and harris.

enter image description here

enter image description here

\$\endgroup\$
2
  • \$\begingroup\$ Not sure what your question is. You probably want to Google for Miller effect and Miller capacity. \$\endgroup\$
    – jippie
    Nov 14, 2015 at 11:54
  • \$\begingroup\$ Miller effect it is - as the article says. In simple terms, the effect of the Miller capacitance is multiplied by the voltage gain of the amplifier stage, which can make it 100x or so worse than the capacitor value suggests. How to avoid it? (1) Cascode (aka Tetrode). (2) Cancel it out with a Neutrodyne... en.wikipedia.org/wiki/Neutrodyne \$\endgroup\$
    – user16324
    Nov 14, 2015 at 13:36

1 Answer 1

1
\$\begingroup\$

Bootstrapping is not really the correct term for this.

MOSFETs all have capacitance between the gate and drain. While some is a parasitic due to the wires, most of it comes from the actual structure of the MOSFET itself.

This capacitance has two effects: When driving the FET via the gate, as the FET turns on and off, the change in voltage across the capacitor is much greater than the change in gate voltage itself (imagine the gate goes from 0 to 5 V, while the drain changes from 48 V to 0.1 V). The current required to do this needs to be driven into the gate, and this makes the capacitance (as it appears at the gate) appear to be larger than just the nominal measured or data sheet value.

The other effect is apparent when a FET is used in an application such as a H-bridge. Imagine what happens to the low-side FET as the high-side FET is turned on. When the low-side is off, its gate-source voltage is low. Now, as the high-side FET turns on and pulls the drain of the low-side FET high, the drain-gate capacitance also tries to pull the gate of the low-side FET up also. If the driver for the low-side isn't strong enough to keep the FET off, the gate voltage on the low-side will rise and it may turn on. If this occurs, both FETs will be on and unwanted shoot-through current will flow, potentially damaging the FETs and certainly wasting power.

A solution for this is to slow down the turn-on of the high-side FET. Generally, fast-operating drivers like this need to be designed to have slow turn-on of the FET and strong turn-off pre drivers.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.