I am starting to learn LTSPICE to create model where I can test various passive filter topologies for inverter drives where the output PWM has very short rise times and high switching frequency.
I have managed to create a model which accurately models the voltage reflection using a PULSE source and a lossless line model.
NETLIST as follows:
V1 N001 0 PULSE(0 20 0.1u 0.1u 0.01n 0.3u 1ms) Rser=50 T1 N001 0 N002 0 Td=0.25US Z0=50 T2 N002 0 N003 0 Td=0.25US Z0=50 R1 N003 0 100 .tran 0 1.8us 0 0.1n .backanno .end
Green: Voltage pulse from source Blue: Measurement between lossless lines Red: Measurement at cable end (motor terminals)
It is seen that the pulse has a travel time from the source to the motor, and that the motor terminal voltage is higher than the source voltage due to the voltage reflection and impedance mismatch (50 vs 100 ohm). The second pulse in the x-axis is the pulse returning to the source.
Now, the problem:
When I add filter components, the voltage essentially drops to zero after the filter. This is what I have implemented: I expected that this would damp the overvoltage. The values are extracted from an IEEE paper (A. von Juanne, "Design considerations for an inverter output filter to mitigate the effects of long motor leads in ASD applications")
The voltage is much lower at the receiving end that what I expected and I hope that someone with better experience than me have some tips to create a model for this scenario.
I got it to work as expected after being more careful with the parameters and components.
The updated netlist:
V1 N001 0 PULSE(0 648 10u 0.025u 0.01n 1.2u 5us 0) Rser=0 R1 N003 0 1MEG L1 N001 N002 0.2m R2 N002 N004 190 C1 N004 0 0.075µ O1 N002 0 N003 0 PL1 .tran 0 501u 0 1n .model PL1 LTRA(len=30 R=6m L=0.36u C=0.01n) .backanno .end
(PS: Dont mind the blue dashed line and 20 % tick, that was just testing)