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I am doing an experiment on Xilinx VC709 board. The experiment involves removing and plugging in the DDR3 RAM while the FPGA is running. But every time I plug back the RAM I have to reprogram the FPGA. I am using JTAG to program the FPGA, which takes time to program. I tried reseting only the Microblaze which still couldn't detect the RAM when plugged back while it's running. Is there any other way that I can reset the configuration without having to reprogram?

Thanks

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    \$\begingroup\$ It's difficult to answer without knowing details of your system - how is everything wired up. But you should have some configuration memory which you can upload your program to (makes reconfiguration faster after resetting the FPGA). Alternatively if you have a DDR controller core, that should have a reset signal which would need to be asserted after the RAM was inserted. Though DDR3 is really not meant to be hot-plugged. \$\endgroup\$ – Tom Carpenter Nov 14 '15 at 19:19
  • \$\begingroup\$ No. You have to reprogram, i.e. reconfigure. But there will be ways to reconfigure from an on-board EEPROM or similar (taking < 1 second), then you only have to program that once using JTAG. It'll involve setting links on the FPGA's mode pins, and selecting the EEPROM in the JTAG chain. See manual for the rest of the details. \$\endgroup\$ – user_1818839 Nov 14 '15 at 19:27
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    \$\begingroup\$ Are you using hot swapable RAM? Inserting RAM (or pretty much any chip) in a powerd circuit may cause latch up and eventually kill the device. \$\endgroup\$ – jippie Nov 15 '15 at 10:42
  • \$\begingroup\$ I am not aware of any sustem that allows you to hot-swap a DDR memory that easily. Are you sure this is what you want to do? \$\endgroup\$ – FarhadA Nov 16 '15 at 17:49
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If you unplug the DDR3 SDRAM module, the configuration insided the module is lost. After the DDR3 SDRAM is plugged in again, the RAM itself must be reinitialized. For example, the desired CAS latency and burst length must be configured (inside the module!) and the DCM (of the module) reset (if used).

This configuration is done by the memory controller, typically after power-up or reset. The FPGA boards from Xilinx etc. typically have a button CPU_RESET (or like) to assert a reset of the whole Microblaze-based system. If pushing this button helps, then you can also trigger the attached signal by your own to restart the system. EDIT: Just restarting the Microblaze is not sufficient, the memory controller must be reset too.

Just restarting the memory controller might also be an option, if the appropiate reset signal is accessible in your design. But, the state of operating system / application would be typically lost anyway.

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The FPGA can be reset by assigning the global set/reset (GSR). This "pin" is automatically assigned after configuration by the configuration FSM and can be user assigned by the STARTUP_* component.

From the Virtex HDL Library Guide:

This design element is used to interface device pins and logic to the Global Set/Reset (GSR) signal, the Global Tristate (GTS) dedicated routing, the internal configuration signals, or the input pins for the SPI PROM if an SPI PROM is used to configure the device. This primitive can also be used to specify a different clock for the device startup sequence at the end of configuring the device, and to access the configuration clock to the internal logic.

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