I am doing an experiment on Xilinx VC709 board. The experiment involves removing and plugging in the DDR3 RAM while the FPGA is running. But every time I plug back the RAM I have to reprogram the FPGA. I am using JTAG to program the FPGA, which takes time to program. I tried reseting only the Microblaze which still couldn't detect the RAM when plugged back while it's running. Is there any other way that I can reset the configuration without having to reprogram?