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Whats the difference between this 2 CLAG (Carry Look Ahead Generator)

CLAG

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Block CLAG

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I mean, the way Carries of 1st 3 bits are the same and the last carry is actually \$G*\$? The difference is use of different gates and the additional \$P*\$ bit?

Equation of 1st image (I'll use 0 index. eg. \$P_0 \text{ to } P_3, C_{-1} \text{ to } C_3\$). Where \$C_{-1}\$ is carry into circuit

\$C_3 = G_3 + P_3 \cdot G_2 + P_3 \cdot P_2 \cdot G_1 + P_3 \cdot P_2 \cdot P_1 \cdot G_0 + P_3 \cdot P_2 \cdot P_1 \cdot P_0 \cdot C_{-1}\$

\$C_2 = G_2 + P_2 \cdot G_1 + P_2 \cdot P_1 \cdot G_0 + P_2 \cdot P_1 \cdot P_0 \cdot C_{-1}\$

\$C_1 = G_1 + P_1 \cdot G_0 + P_1 \cdot P_0 \cdot C_{-1}\$

\$C_0 = G_0 + P_0 \cdot C_{-1}\$

Equation for image 2 ("Block" CLAG)

\$C_1 = (G_1' \cdot (P_1 \cdot G_0)' \cdot (P_1 \cdot P_0 \cdot C_{-1})')'\$

\$= G_1 + (P_1 \cdot G_0) + (P_1 \cdot P_0 \cdot C_{-1}) \rightarrow \textrm{ DeMorgans}\$

So aren't they the same, with the addition of a \$P*\$ bit, or did I miss something?

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They are ALMOST the same.

The difference, as you pointed out, is in fact in P* and G*, that are used to put this Block CLAG in a cascade with others. Basically, the G* out is enabled when the Carry bit result to be generated inside the circuit (in fact, you can see that P* is not added, but created removing the propagate input from the last carry generator G*).

So, instead of creating all the carry bits from the inputs, allows to be stacked and generate the Propagate (P*) and Generate (G*) for the block itself.

The advantage is a simpler logic, because to expand the 4-bit that you have you would have an explosion of signals and gates, that you pay with a (in this case) slower circuit. Note that if you pipeline it in your adder, you will have less routing and less gates, that can result in a faster circuit.

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