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Some questions have already been asked about crystals but there's a few competing designs and I have a few "obsessive" type questions on layout. Here's a almost completed layout with a PIC16F microcontroller connected to a 32.768kHz (12.5pF). Relevant linked questions are:

Competing PCB Crystal layout recommendations

How far is "too far" when routing traces for crystals, and how asymmetrical is "too much"?

Traces under 32kHz Crystal

enter image description here

C22, C23 are 18pF, that's what I came up with after doing: 12.5 * 2 - 2 * stray.

The snap grid on Eagle is 0.5mm.

  • R23 is a resistor I'm undecided about because I see designs with 100k or so and designs without it. That's question 1!

  • I've added a ground fill under the crystal (pins 2 and 3 are unconnected on that particular part) and connected it to local ground only. Olin has mentioned doing that about 100 times so I believe that is the right thing to do. But other designs do a ground ring around the crystal on top layer. Is that only necessary on a single layer board?

  • Pin 6 on the PIC is an digital assert line. I'm hesistant - how close can I bring that trace to the crystal before upsetting the high impedence crystal oscillation? The distance between pins 3 and 4 is 0.7mm approx so it stands to reason (?) that I can be that close?

  • the crystal traces are not equal. Should I make an attempt to make them more equal?

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    \$\begingroup\$ It's been a while since I've done this BUT trying hard is rewarded by fewer marginal results. I'd expect that to work well enough. I'd tend to minimise loop area between xtal & uP - eg run track from C22 up towards C23 before taking it towards IC_pin2. You could consider taking pin2 & 3 traces to inboard ends of C22 and C23 with ground on outboard ends with eg 2 vias to gnd just outside tracks to Xtal pins 1&4. BUT probably doesn't really matter. || X1 could easily slide left towards tracks to PIC with C22 located above/below X1 with shared gnd via under X1. | Best of all is perhaps if .... \$\endgroup\$ – Russell McMahon Nov 15 '15 at 12:09
  • \$\begingroup\$ ... you can rotate X1 90 degrees and move it powards PIC so track length and loop area are now very low. \$\endgroup\$ – Russell McMahon Nov 15 '15 at 12:10
  • \$\begingroup\$ I'll do that with the tracks, thanks Russell. I tried using the inboard ends with 2 vias and also caps above and below with via in the middle as you suggest (but felt they got too close to the PIC) Dithered and couldn't make up my mind :-) I can't rotate because I've a defined limited board area and X1 will fall off the edge! \$\endgroup\$ – carveone Nov 15 '15 at 12:27
  • \$\begingroup\$ I'm thinking that if I keep a trace more than twice its width away from the crystal (so 0.3mm trace is 0.6mm away or about 23 mil), I won't upset the oscillator. I'm also thinking I'm thinking too hard there... \$\endgroup\$ – carveone Nov 15 '15 at 12:57
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If PCB traces start to approach the length of one tenth the wavelength of the crystal frequency then expect problems. At 32 kHz, the wavelength is 9 km so this isn't going to be a problem. Ditto differences in length.

When calculating the capacitances to hang around an oscillator you should take into account the capacitance of the tracks - this will usually be a few pF but you can find online trace-capacitance calculators.

I don't see an issue in what you have shown.

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  • \$\begingroup\$ Thank you. I was really concerned with getting tracks close to the crystal pin. The right angle track from pin 6 is about 0.7mm away. The guides (eg: atmel etc) say "keep changing digital tracks away from the oscillator" without specifying what "away" means. The concern is that you upset the oscillator rather than the other way around but I'm being too paranoid :-) \$\endgroup\$ – carveone Nov 15 '15 at 12:23
  • \$\begingroup\$ I find looking through magazines instructive (or horrifying, depending). EPE June 2015 had a touch screen recorder - PIC32, 32kHz crystal which is just miles away (i.stack.imgur.com/7A1cO.png). If it works for them... \$\endgroup\$ – carveone Nov 16 '15 at 14:00
  • \$\begingroup\$ AN1288 (ww1.microchip.com/downloads/en/AppNotes/01288A.pdf) is helpful too. It concurs: "if traces are short and under 10mm, their capacitance will be very low". The key being capacitance (and crosstalk I suppose) rather than length or difference in length at such a low frequence. \$\endgroup\$ – carveone Nov 20 '15 at 11:41

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