There is something vague with the memory timing operation of 8086 microprocessor as I read from many sources. There is a TAVDV which is the time from when a valid address goes on the bus until a valid data appears on the bus (in the read cycle). Have a look at this book (page 58).
To calculate that (the figure on page 59), it assumes 3 clock cycles as a whole and then subtract two redundant terms. One is the TCLAV which means the time from clock to when valid address is on the bus and the other term is TDVCL which means the time when valid data is on the bus until the edge of the clock.
The idea is pretty simple if you look at those pages. The problem is that the calculation of TDVCL seems to be wrong. Why??
The clock period of 8086 (5 MHz) is 200ns. Since the duty cycle is 30%, that means 133ns for low and 66ns for high is assumed. Therefore,
TCLAV = ONE_PERIOD - Tsetup - T_ONE
I don't know the
200-66=133 and assuming an arbitrary value for
Tsetup, we reach 110ns for TAVCL (as stated in the book).
Now, the book says TDVCL is 30ns. How that is calculated? Data lines must hold valid values according to the
Tsetup. Therefore, in my opinion, TDVCL is absolutely greater than 66ns (which is the time for the clock to be high).
Can someone explain how that is calculated?
I paste the text and figure here