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There is something vague with the memory timing operation of 8086 microprocessor as I read from many sources. There is a TAVDV which is the time from when a valid address goes on the bus until a valid data appears on the bus (in the read cycle). Have a look at this book (page 58).

To calculate that (the figure on page 59), it assumes 3 clock cycles as a whole and then subtract two redundant terms. One is the TCLAV which means the time from clock to when valid address is on the bus and the other term is TDVCL which means the time when valid data is on the bus until the edge of the clock.

The idea is pretty simple if you look at those pages. The problem is that the calculation of TDVCL seems to be wrong. Why??

The clock period of 8086 (5 MHz) is 200ns. Since the duty cycle is 30%, that means 133ns for low and 66ns for high is assumed. Therefore,

TCLAV = ONE_PERIOD - Tsetup - T_ONE

I don't know the Tsetup but 200-66=133 and assuming an arbitrary value for Tsetup, we reach 110ns for TAVCL (as stated in the book).

Now, the book says TDVCL is 30ns. How that is calculated? Data lines must hold valid values according to the Tsetup. Therefore, in my opinion, TDVCL is absolutely greater than 66ns (which is the time for the clock to be high).

Can someone explain how that is calculated?

I paste the text and figure here

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enter image description here

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  • \$\begingroup\$ You do realize you are researching 37 year old technology? I would personally prefer spending my time on more recent technologies. \$\endgroup\$
    – jippie
    Commented Nov 15, 2015 at 19:45
  • \$\begingroup\$ Well, this particular architecture is still tremendously common. I admit I don't know if the specific timings described here are still a thing, but the arch and physical chips are still being made and easy to run into everywhere. \$\endgroup\$
    – user65586
    Commented Nov 15, 2015 at 20:43
  • \$\begingroup\$ The timings aren't relevant for any processor more recent than the 80186 (the 80286 switched a 50% duty cycle clock I believe) ... but the 8086 and 80186 are in fact still in production, and are plausible choices for homebrew computer systems (assuming you don't try to buy them from digikey, who as a non-stockist won't sell less than 99 of them at a time...). \$\endgroup\$
    – Jules
    Commented Jul 17, 2018 at 7:59
  • \$\begingroup\$ "The clock period of 8086 (5 MHz) is 200ns. Since the duty cycle is 30%, that means 133ns for low and 66ns for high is assumed." -- it's generally quoted that the 8086 needs a 33% duty cycle, and this is how most designs actually use them. But a 133ns/66ns clock (usually generated from a 30MHz clock using a counter to 4 then 2 to divide cycles) is actually out of spec, as the minimum low time is given on the datasheet as 69ns. 125ns/75ns (40MHz divided into 5 and 3 cycles) is probably the most reasonable division if you want to stay within spec and get the maximum performance. \$\endgroup\$
    – Jules
    Commented Jul 17, 2018 at 8:19
  • \$\begingroup\$ (See also: retrocomputing.stackexchange.com/questions/5611/… which is sort-of relevant to this question) \$\endgroup\$
    – Jules
    Commented Jul 17, 2018 at 8:33

1 Answer 1

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A google search gives this datasheet.

TDVCL which is the setup time of the data-in flip flop, is a given value which means it is characterized from the silicon, not derived.

TAVCL which is a clock to output value (not a setup value) which is also a given value on the datasheet.

Without knowledge of the internal design you cannot attempt to calculate a value for these, which is why they are given. The fact the TAVCL is so large probably reflects the complexity of the internal asynchronous logic generating the address. It is likely TDVCL is small because the input goes directly to a flip flop.

The two values (TAVLC and TDVCL) can be used to calculate the asynchronous memory access time requirement as done in the book except for the fact they neglected to account for the round trip PCB trace delay.

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  • \$\begingroup\$ "they neglected to account for the round trip PCB trace delay." ... with a 460ns minimum access time and 600ns minimum cycle time, PCB trace delay isn't likely to be a huge concern, unless your board is multiple metres long. \$\endgroup\$
    – Jules
    Commented Jul 17, 2018 at 8:27

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