I am working with an AD7928 (datasheet) and I am a bit confused by the timing diagram (page 25). I would expect to get my first bit off data from DOUT (ADD2) some time after the first falling edge of SCLK after CS' goes low. It would appear t4 may be the dimension that gives this amount of time (40ns maximum). If so, why is the marking from the falling edge of SCLK to the middle of the transition between two bits on DOUT, not to the end of that transition? I would accept that this is simply their convention in diagramming except for the fact that t7 "SCLK to DOUT valid hold time" marked from the falling edge of SCLK to the beginning of the transition between two bits on DOUT? It seems like either t7 should be marked as it is and t4 marked to the end of a transition, or that both should be marked to the middle of a transition. It seems that t7 marks the minimum time for the transition to occur and that t4 marks the maximum amount of time for the transition to occur. Further, why would I even care about t7?

You are correct that T4 is the critical parameter. This defines the timing window that defines valid data, and reading after this time will not guarantee that.

T7 appears informative, in the sense that the next data bit will appear at this time plus any internal setup, transition and settling time. What it does tell me is that you may make no assumptions about what data is on the output in this window between the end of T4 and the end of T7. The output may have valid driven data, but it is unknown as to what that data will be.

T7 is interesting - if you look at the maximum clock frequency (20MHz), that yields a minimum cycle time of 50ns. If you add the time (max) that the data may be held for (T7) and the guaranteed minimum hold time (considering data held on bit n and hold on bit n+1), they add up to that minimum cycle time.

It is highly likely that the internal registers have a 10nsec setup time (certainly the Din timing requires it, see T9), so we have, from Sclk transition at bit n (out):

40nsec max to bit n+1 appearing internally.

10nsec internal setup time (data bit appears at clock transition).

10nsec hold (guaranteed).

So from a clock transition at bit n to guaranteed hold for bit n+1 = 60nsec (max).