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can someone explain the following conditions shown in the image: why condition 1 and condition 2 are there? In condition 1 they have taken the current as Vm/R1 while in the 2nd condition curren is taken as Vm/(R1+R). why?

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  • \$\begingroup\$ You have made some attempt to solve it? you can show us what you did? \$\endgroup\$ – Martin Petrei Nov 16 '15 at 18:13
  • \$\begingroup\$ no, i have written it from a book by P.S. Bimbhra \$\endgroup\$ – Brd Nov 16 '15 at 18:15
  • \$\begingroup\$ i have edited the post and sent the pictures from the book \$\endgroup\$ – Brd Nov 16 '15 at 18:28
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The two conditions, refers to the thyristor on and off.
When the thyristor is off, the gate-cathode voltage is

\$ V_g=\dfrac{V\cdot R}{R_1 + R} \$

(voltage divider).

When the thyristor is on, the resistor \$R\$ is in parallel with gate-cathode on-state resistance, wich usually is very low. Then the value of \$R\$ is negligible.
Therefore, current flows through R1, gate and cathode, and neglecting the voltage drop between gate and cathode:

\$ I_g = \dfrac{V}{R_1} \$

The subscript \$m\$ in the book, corresponds to the maximum value of the signals.

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