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I am trying to understand how to implement up/down binary ripple counter. Basically, I have a bunch of D-flipflops, and connect clk of next flipflop to ether Q or Q'.

So, if I want to change direction of counting, I just switch all clk multiplexors between Q and Q', and counter starts counting in opposite direction.

The problem though is that when I do switch inputs between Q and Q' flipflops do 1 count, so my counter is counting from different number.

I.e. I cannot have something like: 0->1->2->3(direction change)->2->1->0, it's getting like 0->1->2->3(direction change)->c->b->a->9...

What am I missing?

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The key points are:

  • Ensure that after gating the new arrangement makes logical sense. ie why should it count DOWN now. If you don't follow the logic of what you think it should do then you can't be too surprised if it disagrees with you :-)

  • Always change over in a "neutral" state. Ensure that clock lines or other state relevant lines are in a condition before and after the change that will not cause a transient change of state.


A "working" circuit from here

enter image description here

A marvellous (& free) tool

Logisim - an educational tool for designing and simulating digital logic circuits

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  • Logisim is an educational tool for designing and simulating digital logic circuits. With its simple toolbar interface and simulation of circuits as you build them, it is simple enough to facilitate learning the most basic concepts related to logic circuits. With the capacity to build larger circuits from smaller subcircuits, and to draw bundles of wires with a single mouse drag, Logisim can be used (and is used) to design and simulate entire CPUs for educational purposes.
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  • \$\begingroup\$ Thanks, the problem appeared to be that async counters cannot be implemented that easy :-) \$\endgroup\$ – BarsMonster Sep 28 '11 at 5:45
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If you want a ripple counter that count bidirectionally, it's possible to implement a bidirectional quadrature-input gray-code counter using entirely level-sensitive latches. The top two bits of a stage can feed into the next stage. Even if one of the inputs goes metastable for awhile, the counter will behave provided that the metastable input stabilizes before the other input changes.

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  • \$\begingroup\$ Doh, yeah, apparently it's a bit more complicated than I've thought :-) \$\endgroup\$ – BarsMonster Sep 28 '11 at 5:44
  • \$\begingroup\$ @BarsMonster: I rather like the design of a bidirectional quadrature graycode counter, though another approach is to simply have a pair of ripple counters--one that counts "up" pulses and one that counts "down" pulses. Trying to design a normal asynchronous ripple counter that can handle asynchronous "up" and "down" events is problematic because near-simultaneous "up" and "down" events should cancel, but it's hard to ensure that they will do so. \$\endgroup\$ – supercat Sep 28 '11 at 12:58
  • \$\begingroup\$ Well, in my case, I can only use a handful of NAND gates, so complex things sounds scary. In my case, I can be sure that up and down pulses have sufficient time intervals between them so that all logic can settle. \$\endgroup\$ – BarsMonster Sep 28 '11 at 13:13

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