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I have a 10Gbps NRZ signal generated which is to be fed into a 4:1 MUX. The system contains three components: The serial link chip consists of three individual macros: transmitter , receiver , and a PC Enhanced Parallel Port (EPP) interface. Transmitter consists of a 4:1 multiplexer (MUX) and an 8 tap finite impulse response (FIR) filter.
The link operates at 10 GHz, which is faster than typical CMOS clock speeds for this process, multiplexing is required to combine slower data into one 10 GHz bit stream. Assuming the CMOS clock is 2.5 GHz, the CML 4x1 multiplexer drives four bits every 2.5 GHz cycle. Four 2.5 GHz clock phases are the selection signals to the multiplexer. For example, when phases 0 and 1 are high, bit 0 is selected by the multiplexer. When phases 1 and 2 are high, bit 1 is selected.
Question1: How to drive the 4:1 multiplexer with four bits every 2.5 GHz cycle and 10/4 Gbps signal as input to each of the 4 channels and also do the reverse at the receiver which has a 1:4 demultiplexer? Is there a general circuit/rule so that the same can be applied to MUX of other categories for different bit rate?
Question2: Is this also called serialization? What is the difference between serialization and the function of MUX?
Question3 : Is there a requirement of an ADC convertor and PLL /DLL for connecting the transmitter and receiver?
Question4 : What shall be the value of the parameter number of Samples in the Discrete Eye Diagram block for a signal of 10Gbps?