# memory interfacing with banks [closed]

In the concept of memory interfacing (cpu<=>memory), it is desirable to have two banks for odd and even addresses. The reason goes back to the history when manufacturers increased data bus width from 8-bit. So, they decided to put odd addresses on one bank and put even addresses in the even bank.

            ODD                       EVEN
D15     D8                D7        D0
+-----------+             +------------+
00001 |           |       00000 |            |
+-----------+             +------------+
00003 |           |       00002 |            |
+-----------+             +------------+
00005 |           |       00004 |            |
+-----------+             +------------+
|  ....     |             |     ....   |
+-----------+             +------------+