Recently, I've played with a simple 2-input 1-output NAND gate realised in CMOS technology as shown in Fig. 1.
Fig. 1. CMOS NAND scheme.
I took some measurements of volteges U(output) vs. U(input). Using two independent voltage sources (constant high level Udd and Uin varying in 0-to-Udd range), I considered three different connection possibilities so to investigate all four input configurations. Those were:
a) Input terminal A connected to Udd, input terminal B connected to Uin.
b) Input terminal A connected to Uin, input terminal B connected to Udd.
c) Both input terminals connected to Uin.
I've obtained following characteristics:
Fig. 2. CMOS NAND voltage characteristics with different connection methods.
As long as a difference between case c) and other cases I could have expected, I was surprised to see a) and b) differ as well. Could someone please explain to me why would changing voltages connection between A and B significantly changes threshold voltage of the gate? Is it a widely observed effect or have I just picked a defective NAND?