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This is what I have, but I not sure if it's right. Can someone please help me. Thanks in advance

Q A B | Q(t+1)

0 0 0 | 1

0 0 1 | 0

0 1 0 | 0

0 1 1 | 1

1 0 0 | 0

1 0 1 | 1

1 1 0 | 1

1 1 1 | 0

  • \$\begingroup\$ Check the line 1 0 0 | 0. \$\endgroup\$ – Tom Carpenter Nov 22 '15 at 17:07
  • \$\begingroup\$ Might help to include Q_bar in your truth table to help see what is going on. \$\endgroup\$ – Tom Carpenter Nov 22 '15 at 17:10
  • \$\begingroup\$ Thank you @TomCarpenter. Can u please tell me if everything else is right? Again thank you so much \$\endgroup\$ – Abhi Nov 22 '15 at 17:10
  • \$\begingroup\$ There are three more lines which are wrong as far as I can tell. \$\endgroup\$ – Tom Carpenter Nov 22 '15 at 17:12
  • \$\begingroup\$ Is it a D-Latch? Never mind. \$\endgroup\$ – ammar.cma Nov 22 '15 at 17:36

The table is not correct. It is roughly half right.

My suggestion is to start in each state (so with the inputs and Q as you show in your table), then work through from left to right seeing what happens. You can write on the diagram what level each wire is as you go.

For each state, you should work through once, then once you have the levels of each wire written down, work through it again based on the levels for the wires you have written down in the previous go (not the original values). In fact keep going through until none of the wires change value. The NAND gates at the end are a bit awkward as they change their inputs, so you have to recalculate until it settles.

Here is an example for the state when Q=0, A=0 and B=0. Each diagram shows one pass.

In the first diagram, the Red numbers are the inputs, the Green numbers are calculated during the pass. Another pass is required to make sure nothing has changed because the logic is not combinational - the outputs feed back into the circuit.

In the second diagram, I've worked through the circuit and calculated the values again for each gate (starting from the inputs and working forward). Notice how the value for Q changed, you will note that the value for Q is actually wrong in the first diagram because the inputs to that NAND gate have changed from whatever they were before this state was entered. Because a gate changed, we now need to recalculate a third time.

In the third diagram, I did another pass, and notice that now Q_bar has changed. Again because its inputs changed in our previous pass. You know what that means... need to recalculate again.

In the fourth pass, nothing changed. Yay, the circuit is stable, so we know what the new outputs are now.

State 000

In this circuit you shouldn't find this next situation, but in others you may... if when running through you discover that you have reached a state that you have been in before - e.g. if you do this analysis on a NOT gate connected back on itself - then you have formed an oscillator and you might as well stop because the circuit is never going to stabilise.

  • \$\begingroup\$ Thank you so much, but i'm still confused can you please give me one example when input is 0 0 0. Please thank you \$\endgroup\$ – Abhi Nov 22 '15 at 17:24
  • \$\begingroup\$ @AP6 I've added an example as requested. \$\endgroup\$ – Tom Carpenter Nov 22 '15 at 17:39

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