Also there is a lot of history involved.
Many chip layouts are designed to be a close match for previous generation chips so they can be used optionally on the same or next board revision. The 1 kB to 64kB ROM/PROM/SRAM/EPROM/EEPROM chip layouts spanned many generations and the early generations had chip design restrictions that are long forgotten.
The chip designers take cognisance of what customers want and if customers only purchased chips with neatly ordered data and address pins then that is what would be in the shops. As it is the layout maybe exactly what people want and this may not be obvious without years or experience routing boards to save a few cents here and there.
Modern Gate arrays that allow designers to pick almost any pin for any function have made board routing simpler but it can never be a one to one match for every combination of random chips a designer uses.
The large bulk of 16 bit systems used 8 bit memory for a long time as it was the standard available. It is cheaper to put in a bigger 8 bit chip than two smaller 8 bit memories just to get a 16 bit bus width. The same way you save 32 pins on the chip carrier if you multiplex your 64 bit data into two cycles instead of trying to have everything on the bus wired for 64 bits when some of the buses, chips or peripherals cannot even use 64 bits. But more importantly if you can multiplex the data lines (address lines in dynamic RAM are also often multiplexed) you can save a lot of pins and this saves a lot on board routing and size and chip size and cost and and and.