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I'm using Cadence Virtuoso 6.1.6 and am trying to design a ring oscillator using CMOS inverters. I have looked at other questions that have been asked on this forum, but I wasn't able to find any that were designed using Cadence.

A little background - I have been tasked with making a "VCO" using "sgfet" CMOS transistors. These "sgfet" transistors are very similar to regular CMOS transistors. The only difference is that these transistors are cylindrical as opposed to having a width and length. But their behaviour is exactly the same as regular CMOS transistors.

I strung three inverters together to create the ring oscillator as follows -

Ring Oscillator in sgfet technology

The capacitors I used between the inverters are both 10nF (I'm not sure if these are necessary or not).

Once I ran the simulation, I get the following output -

Damped oscillations

Why am I not able to get an undamped output? I have tried almost everything I can. Please help!

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    \$\begingroup\$ I removed all the capacitors and I added a pulse source between the output and input (in the feedback path essentially). I got the oscillator to work. Here is the final output - imgur.com/XbBK12R \$\endgroup\$ – ragzputin Nov 23 '15 at 19:33
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I just saw that you only have 2 capacitors in the circuit.

If they are large (say over 1000x the input capacitance of the inverters), then this won't work. Basically, the phase shift of each inverter driving a capacitor needs to reach nearly 90 deg (if the 3rd inverter had no capacitive load, its phase shift will be small) so that the total can reach 180 degrees.

If the capacitors are only on 2 inverters, by the time these reach nearly 90 degrees phase shift, the attenuation will be large (say 10x); the remaining inverter is unlikely to have a gain over 100x, and so the total loop gain will be < 1, and it won't oscillate.

So -- put a 3rd capacitor and it'll oscillate at the point where each stage has 60 degrees of phase.

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  • \$\begingroup\$ Right now the circuit is powered by a constant supply of Vdd = 1V for all the inverters. How do I make different supplies that run at different rates? \$\endgroup\$ – ragzputin Nov 23 '15 at 1:17
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    \$\begingroup\$ I changed the Vdd of one of the inverters to 0.8V instead of 1V. Still getting the same output. \$\endgroup\$ – ragzputin Nov 23 '15 at 1:35
  • \$\begingroup\$ None of your solutions work... \$\endgroup\$ – ragzputin Nov 23 '15 at 3:50
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    \$\begingroup\$ Why dont you simulate the loop gain (oscillation condition)? \$\endgroup\$ – LvW Nov 23 '15 at 7:43
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    \$\begingroup\$ That's not a transfer function -- it's a transient response. Send a slow triangular ramp to the inverter and plot input and output \$\endgroup\$ – jp314 Nov 24 '15 at 1:28
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I don't know what Virtuoso specifically does, but most circuit simulators I have used run a DC operating point find first. This seems to be settling down around mid-rail.

Set an initial condition of one of the nodes. The transistor/gate models may not have such a parameter, but your shunt node capacitors certainly will, which will force the circuit to start.

I've just noticed you, you have extra C on only 2 of your three nodes, put C on all three.

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  • \$\begingroup\$ I set an initial condition lots of times for the feedback loop...didn't work at all. \$\endgroup\$ – ragzputin Nov 23 '15 at 6:19

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