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I would like to use a FIFO in VHDL, I used coregen to make it but when I want to use it into my project, I get this error :

ERROR:NgdBuild:604 - logical block 'U101' with type 'fifo_generator_v9_3' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'fifo_generator_v9_3' is not supported in target 'spartan3a'.

I can't find where this error come from... Here's some parts of my code (those with the FIFO) :

component fifo_generator_v9_3 is
PORT (
        M_CLK : IN STD_LOGIC;
        rst : IN STD_LOGIC;
        din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
        wr_en : IN STD_LOGIC;
        rd_en : IN STD_LOGIC;
        dout : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
        full : OUT STD_LOGIC;
        empty : OUT STD_LOGIC
        );
end component;


signal WRITE_EN, READ_EN, FIFO_FULL, FIFO_EMPTY : STD_LOGIC;
signal DATA_IN, DATA_OUT : STD_LOGIC_VECTOR(17 downto 0);

U101:fifo_generator_v9_3
port map (
            M_CLK,
            rst,
            DATA_IN,
            WRITE_EN,
            READ_EN,
            DATA_OUT,
            FIFO_FULL,
            FIFO_EMPTY
            );

Q : Can someone tell me where that error come from (in my case) ? Is it possible that I'm missing a file? In that case, where can I find it?

Thanks in advance !

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  • \$\begingroup\$ Does this error pop up during simulation? Which simulator? \$\endgroup\$
    – Botnic
    Nov 23, 2015 at 10:39
  • \$\begingroup\$ No, it doesn't pop up during simulation, it appears when I try to implement the design using ISE 14.7 (Spartan 3AN) \$\endgroup\$
    – Cabs
    Nov 23, 2015 at 10:50
  • 2
    \$\begingroup\$ @Botnic : NGDbuild is not a simulator! To answer the question : You need to add the Coregen path to the search paths so that Translate/Map/Par can find the actual block that implements the fifo_generator component. Or move the fifo_generator_*.ngc file to the project directory. \$\endgroup\$
    – user16324
    Nov 23, 2015 at 10:52
  • \$\begingroup\$ Thank you @BrianDrummond ! It was that, seems logical but hard to know for my first FIFO implementation... Why do you dont' post it as an answer? \$\endgroup\$
    – Cabs
    Nov 23, 2015 at 12:10
  • 2
    \$\begingroup\$ An alternative solution is to run CoreGen inside of ISE, in that case, the coregen file (*.xco) would be linked to the project and no search path is needed. I prefer @BrianDrummond 's way, because it's more flexible and advanced :). You should also set the search path for XST (copy the '-sd ....' line(s)). \$\endgroup\$
    – Paebbels
    Nov 23, 2015 at 13:24

1 Answer 1

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Ok so the right answer was (as Brian Drummond said) that I needed to add the Coregen path to the search paths or I could move the fifo_generator9_3.ngc file to my project directory, I did the second one and it works !

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