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I see that a lot ICs for PC use a single 14.318 MHz crystal oscillator (which is an NTSC standard frequency, so very widely available in terms of parts) to generate the clocks for PCI, USB, etc. Here's a table from one such chip, ICS932S421B.

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How does this work? These don't seem obvious multiples.


I found an older datasheet RTM520-39 that at least has clue for the 33.33 MHz (but not for 48.000 MHz): 149/16 * 14.318 = 133.34, which divided by 4 gives a decent 33.3341 MHz PCI clock. For USB it said that it used 107/16 * 14.318 = 95.75 MHz and then divided by 2.

Also worth noting here is that more recent PC ICs, e.g. SLG84901, use a 25 MHz reference clock, which surely makes PCI Express (100 MHz) clock generation simpler.

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  • \$\begingroup\$ Look for PLL phase locked loop, the frequency is output with voltage controlled oscilator VCO, then divided and compared with base frequency (feedback). \$\endgroup\$ Nov 24 '15 at 9:40
  • \$\begingroup\$ @Marko Buršič: Yeah, I know the general theory, but what frequencies goes into those dividers in that block diagram? \$\endgroup\$
    – Fizz
    Nov 24 '15 at 9:50
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Well, you can't get exact frequencies from 14.318, but you can get approximations. For example, 14.318*7/3 = 33.408 and 14.318*10/3 = 47.727.

You can get closer with larger fractions. 14.31818 * 352 / 105 = 47.99999390476, which is 6.095238 Hz off of 48 MHz with an error of 6/48 = 0.125 ppm. That's far better than what the crystal will be. Now, I'm not sure exactly how that ratio would be implemented in the PLL. I can think of 4 possibilities offhand: VCO of 48 MHz, VCO divided by 352 and reference divided by 105 for 136.363 kHz. VCO of 240 MHz, VCO divided by 5 for output and 352 for loop, reference divided by 21 for 681.818 kHz. VCO of 720 MHz, divided by 15 for output and 352 for loop, reference divided by 7 for 2.045454 MHz. Or VCO of 1008 MHz, divided by 21 for output and 352 for loop, reference divided by 5 for 2.863636 MHz.

The other outputs would be something similar.

Edit: Here is a page for approximating fractions: http://www.mindspring.com/~alanh/fracs.html . If you put in 3.352381378080175 (48/1.31818), it will generate a list of approximations of increasing accuracy. And 352/105 is probably the most reasonable one, as the terms are relatively small and the result is quite accurate. Now, doing a two-stage PLL is also possible, but not quite as straightforward as the intermediate frequency has to be selected somehow.

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  • \$\begingroup\$ Claims to output exact 48.000MHz though. \$\endgroup\$
    – Fizz
    Nov 24 '15 at 9:46
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    \$\begingroup\$ It says 100 ppm error, so it might not be exactly exact. \$\endgroup\$ Nov 24 '15 at 9:48
  • \$\begingroup\$ It says that for all other clocks. \$\endgroup\$
    – Fizz
    Nov 24 '15 at 9:48
  • \$\begingroup\$ @Arsenal The reference frequency is actually specified as 14.31818 MHz. \$\endgroup\$ Nov 24 '15 at 10:14
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    \$\begingroup\$ Yeah, I don't usually bother with wolfram alpha. I usually just use ipython as a scientific calculator. I found that 352/105 ratio by starting with 48/14.31818 and then multiplying by small numbers until I got something close to an integer. Not sure if there is a simpler way to do that or not. It would be nice to have a tool to get approximate integer ratios that lists out a bunch of possibilities with the corresponding error. \$\endgroup\$ Nov 24 '15 at 10:36
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There are a number of techniques used to synthesize frequencies using a PLL. The most straightforward is the integer divider/multiplier technique. Another is the fractional multiplier/divider, but it is more complicated.

For a standard crystal trimmed out to 14.318 MHz the integer synthesis technique can produce a 48.000 MHz output by dividing the input frequency down by 7159 to 2 kHz. With a VCO output of 48 MHz divided down by 20000 also results in a 2 kHz frequency. The divided reference and divided VCO are used to drive a phase comparator that adjusts the VCO to stay in sync with the crystal. An actual practical solution may very well use a couple of stages of up convert to reduce the overall multiplier of the VCO.

If one wants to be more technical a standard "NTSC crystal" would be more like 14.31818 MHz. In this case the design is just not practical at all because the phase comparator frequency would be only 20 Hz with a reference divider of 715909 and a VCO divider of 240000.

Helpful calculator link.

To follow up on the idea of using two PLLs in series one could start with the 14.318 MHz and divide that by 7159 to 2 kHz. A VCO at 6 MHz could operate with this with its feedback divider being 3000.

The second PLL could then be a simple up convert to 48 MHz using a feedback divider around the VCO of 8 to result in a 6 MHz signal to phase compare against the first VCO output.

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I've used Cypress' CyberClocks software to see what it would suggest for getting 48.000MHz out of 14.31818MHz clock. Its solution was to get a 288 MHz VCO (actually 287.999963 MHz) and divide that by 6. This is not actually exact (as claimed in the ICS datasheet, which still remains mysterious in that respect), but it's pretty good, with a PPM of -0.1.

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The P & Q calculator for that VCO value gives P=704 and Q=35.

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This 704/35 sounds a lot more plausible than dividing by several thousands or even by hundreds. If I actually ask/force the PPM to 0 for 48MHz it gives/says no solution. Some fractional PLL might be capable of this, but I rather doubt anyone implemented that just for USB.

Actually 704/(35*6) = 704/210 = 352/105 which is what alex.forencich proposed; it's just a different implementation of that. The actual PPM error for this is 0.127. I guess that might be "exact" for some marketing types. Actually if 14.31818 is just an approximation for 14.3(18)=315/22 i.e. that's a period, then it looks like this solution is exact. And a bit of googling finds some sources (e.g. 1 or 2) that say the actual NTSC frequency is indeed 315/22 MHz.

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