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So I'm pretty new to Verilog and am working on a 3 bit multiplier project that outputs the decimal solution of the multiplier to the 7 segment display on my fpga board. I'm having a problem with conceptualizing how exactly my counter module that was given to me would allow me to switch in between inputs. The counter looks likes this:

module counter (
input clk,
output [1:0]Y
);

reg [24:0] counter;

always @ (posedge clk) 
begin
counter <= counter + 1;
end

assign Y[1] = counter[24];
assign Y[0] = counter[23];

endmodule

I feel like I either need to use a 2:1 mux or a latch. I've started my code and it looks like this:

module cath_mux(
input clk,
input [3:0]ones,
input [3:0]tens,
output [3:0] disp
);

reg [3:0] disp;
wire [1:0] Y;

counter count(.clk(clk), .Y(Y));

always @ (Y)
begin
case (Y)


endmodule   

I'm just not sure how to set up my case statements since there would be 4 cases with a 2 bit array for Y. The inputs come from a BCD decoder and the output would go to a module that will change my cathode values based on my BCD digit fed into it from the output of this module. I also need to figure out how to use the counter module to switch between active anodes on my board too.

This question seemed similar but I'm not sure how it applies to my question.

https://electronics.stackexchange.com/questions/165609/verilog-for-4-bit-wide-21-parameterized-mux-output-needs-to-be-decoded-to-7-se

Our logic circuits professor has been gone for two weeks and no one in our class has been able to really figure this out. Any suggestions or help would be really appreciated!

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  • \$\begingroup\$ Its good that people are honest about homework. \$\endgroup\$ – Autistic Nov 24 '15 at 10:29
  • \$\begingroup\$ Y is either 0, 1, 2, or 3 (it's a 2bit number). I'm sure you can set up your case statement with those options. Then for each case, what should disp be? \$\endgroup\$ – Tom Carpenter Nov 28 '15 at 21:52
  • \$\begingroup\$ So since I was using a BCD decoder to output my ones and tens values I only needed two values for Y. So the counter module I was given was actually giving too many values. I only needed Y to be switching between on and off. My cases should then just be for 0,1 and they just evaluate to the ones value and assigned anode, then the tens value and assigned anode. \$\endgroup\$ – Nick Nelson Dec 1 '15 at 7:25
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Then why would you use 2 bits for Y. If you only need two possible outcomes just use a single bit Y = counter [24];, Also you need to have a reset in the counter module so that you can initialize the counter to zero or else it's value will remain XX.

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