# Event Driven Simulation: Confusion

I was reading about event driven simulation. Such simulations proceed after we have an 'event' which is the change in any signal value at the input of any design being simulated. The list of all the changed signals is added to what is called an 'event queue'. An 'event driver' then figures out what gates have these signals (inside the event queue) as input which in turn is passed to a 'gate driver'which calculates the output of the gates and stores the output in the new event queue. This constitutes one time step at the end of which signals in the event queue are assigned to the respective nets.
(For further details:http://cs.baylor.edu/~maurer/aida/desauto/chapter3.pdf)

Thus, I inferred that the signal assignments to the nets are always done at the end of each time step.

always @ (a or b or c)
begin
x = a | b;
y = a ^ b ^ c;
z = b & ~c;
end


Since in blocking assignments evaluation and assignments are immediate. Does this mean that say if a changes then each assignment will take place in one time step and hence the whole series of assignments, of x, y and z, takes three time steps?
Further, since it is an event driven simulation. If only c changes, the assignment of x will not take place, since there is no c in the inputs, and the assignments will take two time steps?
EDIT
Based on the answer below I agree that the assignments will be happening in a single time step. But consider the circuit below:

In the document I mentioned it is said that the assignments at C and Q will take place in two time steps. But suppose I code the circuit as follows:

always @ (A or B)
begin
C=~B;
Q=A&C;
end


Shouldn't the assignments at C and Q take place in a single time step?

• The gold standard for this is the model VHDL uses, which guarantees determinism. Understanding it might help you understand the Verilog approach somewhat better. stackoverflow.com/questions/13954193/… Sorry I can't help with the specifics of Verilog but I suggest searching "Cliff Cummins non-blocking assignments" to find his authoritative paper on it. – Brian Drummond Nov 24 '15 at 11:44

Verilog, is a hardware descriptive language. So think from hardware perspective which, in the ideal case do not have any delays (though setup,hold etc. many delays are present).

Referring the code snippet, the always block will execute whenever there is any change in either a or b or c.

A blocking statement must be executed before the execution of the statements that follow it in a sequential block.

Non blocking statements allow you to schedule assignments without blocking the procedural flow.

Blocking and non-blocking assignments are better understood by following example:

x = #10 5;   // x = 5 at time 10ns
y = #5  6;   // y = 6 at time 15ns

x <= #10 5;  // y = 6 at time 10ns
y <= #5  6;  // y = 6 at time 5ns


Here, in blocking assignment, y is evaluated after x is assigned a value. While using non-blocking assignment, x and y are evaluated and pushed into simulators internal queue and assigned at 10ns and 5ns respectively.

A blocking assignment effects immediately. A nonblocking assignment takes place at the end of processing the current "time delta".

In Verilog, there is a well defined event queue as shown below. For each and every timestamp, all the regions are evaluated. If there are any events to be executed in current timestamp, then they are triggered. Once all the events of current timestamp are triggered, then only simulation time moves forward.

Coming to your example, if a changes, always block is triggered and ALL the statements are in always block are executed. x, y,z are assigned the values immediately. This all happens in ACTIVE REGION of same timestamp. Even one of he variable in sensitivity list changes, all the statements are in the block are executed.

Refer Blocking-Nonblocking difference, Cummings_Verilog_Nonblocking paper, and Event Regions paper for further information.

EDIT:

The pdf Page-7 says :

the basic event-driven technique provides a unit-delay model, in which the delay of each gate is assumed to be one.

The Unit delay Model assumes implicit 1 timestamp delay for calculation output of every gate. This is indeed true, since physical hardware shall have certain finite delay, thus justifying:

Simulated time increases by one for each subsequent execution of the Event Processor.

Also, this is just a general assumption, the time unit of delay varies according to time scale. While the above code refers to ideal condition output that a simulator shall produce (that is, with zero gate delay).

Referring to PDF again:

The two-phase structure of the event-driven simulation algorithm imposes a time scale on the simulation...It is usually assumed that an arbitrary number of simulated time units can occur between successive input vectors.

For the circuit, if both A and B changes, then according to event driven simulation model, G2 is evaluated since A has changed, at lets say at 0ns. Along with G2, G1 is also evaluated due to B at 0ns. Thereafter, G2 is evaluated once again due to C at 1ns, producing output at 2ns.

If either A or B changes, then G2 is evaluated once, since either of A or C shall change. If only B has changed, then it must take 2ns delay while changing A shall result in 1ns delay.

Refer to this and this material for further info.

• Thanks...Would this mean that if the code looked like this always @ (a or b or c) begin x = a | b; y = a ^ b ^ x; end Where y now depends on x, the value of y would be indeterminate or will have a race condition, depending on which statement is executed first? – sarthak Nov 24 '15 at 12:10
• Here, blocking assignment is used. So, going into sequence, x is evaluated and updated first. Then y is evaluated, so there is no in-determination. – sharvil111 Nov 24 '15 at 12:15
• In this document:cs.baylor.edu/~maurer/aida/desauto/chapter3.pdf at page 7 it says that it will take 2 time steps to execute the assignments, at C and Q. If I use blocking statements for both the gates inside an always block, should this then execute in single time step? – sarthak Nov 24 '15 at 12:31
• @sarthak I have edited the answer accordingly. – sharvil111 Nov 24 '15 at 14:12
• What should be the code that produces 2 time step delay? Further I do not think that unit delay is assumed for the model, it is because of the way it is implemented unit delay is arising. – sarthak Nov 24 '15 at 14:43