On my board, I'd like to replace an RJ45 port with an SFP+ transceiver to increase data rate to 10Gbps. In choosing an SFP+ module, I have noticed that the only MSA compliant interfaces can be limiting, linear, or both, while I see re-timed interface(existing in XFP and some non-compliant SFP+ modules) is recommended for communicating with some FPGAs. I'm looking at finisar(FTLX8571D3BCV) and xilinx kintex-7 to communicate with. Does the lack of CDR module cause problems?

I'm a newbie in these fields, so please let me know if more info in needed to clarify.

  • \$\begingroup\$ Concerned by your question, Martin Zabel and I investigated retimed modules. As was as we know retimed modules used e.g. XFP connectors which provided a differential clock pair for the transmitter and receiver for retiming. The XFP standard is outdated and (Q)SFP+ is nowadays used. We tested a board-to-board connection from KC705 to VC707 over 2 SFP-to-SATA adapters and 1 m SATA cross over cable @ 10 GHz. It works. So the transceivers are good enough to handle the electrical interface. \$\endgroup\$ – Paebbels Nov 30 '15 at 13:38
  • \$\begingroup\$ How can I test my sfp+ module with an FPGA (say a zynq 7000)? Could you guide me to any document/tutorial or steps to set up a test? I'm thinking about feeding the Rx with signal generator and connecting an oscilloscope to the Tx end while using a loopback on the SFP+ module, but I really haven't found more in-detail steps or information regarding test parameters and setup. \$\endgroup\$ – Arash Dec 4 '15 at 19:17
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    \$\begingroup\$ We used the Xilinx Core Generator to create PCS 10GBASE-R core. This core comes with an example design (frame generator + checker). We just needed to change the ref clock pins and UCF file entries to match our boards. Xilinx offers a LogiCore IP block user guide for a coarse overview. The 10GBASE-SR modules are ordered. \$\endgroup\$ – Paebbels Dec 4 '15 at 21:46

I don't think it is that easily.

The SFP+ requires an FPGA with a high speed transceiver. Not all FPGAs have those available and the ones who have (like Virtex-7) are usually not connected to the RJ45 connector of the development board.

In order to be able to have such functionality, you either need an FPGA board that is already have a SFP+ like this board: Xilinx Virtex™ 6 PCI Express Gen 2 / SFP / USB 3.0  Development Board From High-Tech Global. Or purchase a board like this one: Xilinx Dual SFP+ expansion board From Xilinx: http://www.xilinx.com/products/boards-and-kits/1-3y8uy5.html

  • \$\begingroup\$ Thanks Farhad. We do plan to use a series 7 zynq xilinx FPGA chip which will have high speed transceivers. The host board is designed by us however. I know the implementation is doable but I have not been able to find enough information regarding the differences in design for various interfaces. \$\endgroup\$ – Arash Nov 25 '15 at 15:31
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    \$\begingroup\$ If you are planning to make the design yourself, then you need to look into the guidelines Xilinx has made available for board design as well as FPGA design. "UG476-7Series Transceivers guide" is one of the good starting points. As for more in depth look into usage of multi-giga-bit transceivers, you can take a look at this powerpoint presentation from Xilinx www.keysight.com/upload/cmc_upload/All/5XilinxTheDos.pdf it is not spefic for any FPGA and should be usefull for you too. \$\endgroup\$ – FarhadA Nov 26 '15 at 8:30
  • \$\begingroup\$ @FarhadA, i am going to use SFP+ with Lattice ECP5M, 3.2Gbps transceivers. Is it going to work for PCIe (2.5Gbps)? \$\endgroup\$ – Gregory Kornblum Mar 15 '16 at 16:30

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