How is the electrical bus capacitance for I2C trace calculated?

Question

i am trying to learn how to calculate the bus capacitance of an I2C tree with a master and multiple slaves.

For example, in this document from TI, it shows how to calculate the value of the pull up resistors and just assumes the captive load of each bus line to be 400 pF.

Where do I get this pF number in my i2c design?

What I can think off is two sources (what am I missing?):

1. I need to look up specs of all slave devices and add up their Capacitances to be in parallel, right?
2. The second source would be the I2C trace itself, right? If my trace is let's say 6 inches long, how do I calculate the capacitance of this trace?

Answer 1

How is the electrical bus capacitance for I2C trace calculated?

It isn't. You either guess and check, or design to tolerate as much as possible.

Where did 400 pF come from? Whoever wrote that app note pulled it out of thin air, figuring that's a "large" number, but still makes everything work out right with the parts he's trying to show you how wonderful they are.

400 pF does sound quite high for even a long trace on a large board, so it's about as good a number as any. Of course the only way to know for sure is to measure your particular case.

However, the better strategy when you're worried you're hitting this limit is to use the smallest pullups possible to not exceed the maximum current a node must be able to sink when holding a bus line low. That's the best you can do, so now it's up to bus speed to adjust to whatever capacitance you actually have.

For example, let's say this is a normal IIC bus where the maximum sink current per line is 3 mA. (3.3 V)/(3 mA) = 1.1 kΩ, which is the lowest pullup you can use with 3.3 V power. Let's say a line really does have 400 pF parasitic capacitance to ground on it. The pullup and this capacitance form a R-C low pass filter with a time constant of (1.1 kΩ)(400 pF) = 440 ns. I don't remember off the top of my head what the guaranteed logic high level is for IIC (your job to look up), so let's use 2.0 V as example. It takes .93 time contants for the R-C filter to rise from 0 to 2.0 V, which is 410 ns. That's how long it takes after a 1 is "written" to the bus before all devices are guaranteed to see it as a 1. Obviously you need the half-bit time to be a bit longer than that. At 410 ns half-bit time, you have 820 ns bit time, or 1.2 MHz maximum clock rate. Again, you want some margin. A factor of 2 would be nice, so you might consider 600 kHz as the upper clock rate limit. Basic IIC slaves can have 400 kHz as their upper limit, which this bus should work fine at.

Again, remember that some numbers were made up in this example. It's your job to check all the relevant specs and substitute the correct values. I am only trying to show how to go about the calculations.

Answer 2

The I2C is a bus to connect to multiple slaves. These slaves can be other MCUs or could be sensors (gyro,accelo,...etc). Now each pin of the slave(which is connected to the bus) has its own capacitance and loads the line with that value. For microcontrollers its usually a few picoFarads. Check out the datasheet. Now, these can be modeled as small capacitors in parallel(for each slave/master in the bus).

Now, we have traces connecting these buses and these have its own impedance(capacitive and inductive). You can forget inductive as they come to play only at high frequencies and not I2C ones. The capacitance of these tracks can be calculated using tools like Saturn PCB or Agilent to get a rough estimate of the capacitive loading on your bus.